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ORCID23rd COOL CHIPS 2020: Kokubunji, Japan
- 2020 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2020, Kokubunji, Japan, April 15-17, 2020. IEEE 2020, ISBN 978-1-7281-6347-5
- Masayuki Sato, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi:
Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture. 1-3 - Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda:
Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. 1-3 - Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner:
A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. 1-3 - Yasuhiro Mochida, Takahiro Yamaguchi, Ken Nakamura:
MMT-based Multi-channel Video Transmission System with Synchronous Processing Architecture. 1-3 - Jisu Kwon, Moon Gi Seok, Daejin Park:
User Insensible Sliding Firmware Update Technique for Flash-Area/Time-Cost Reduction toward Low-Power Embedded Software Replacement. 1-3 - Dionysios Diamantopoulos, Florian Scheidegger
, Stefan Mach, Fabian Schuiki, Germain Haugou, Michael Schaffner, Frank K. Gürkaynak, Christoph Hagleitner, A. Cristiano I. Malossi, Luca Benini:
XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs. 1-3 - Takuya Sakuma, Hiroki Matsutani:
An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection. 1-3 - Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers. 1-3 - Haerang Choi, Yosep Lee, Jae-Joon Kim, Sungjoo Yoo:
A Novel In-DRAM Accelerator Architecture for Binary Neural Network. 1-3 - Meenatchi Jagasivamani, Candace Walden, Devesh Singh, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce L. Jacob, Donald Yeung:
Tileable Monolithic ReRAM Memory Design. 1-3 - Shota Nakabeppu, Yosuke Ide, Masahiko Takahashi, Yuta Tsukahara, Hiromi Suzuki, Haruki Shishido, Nobuyuki Yamasaki:
Space Responsive Multithreaded Processor (SRMTP) for Spacecraft Control. 1-3 - Markus Hiienkari, Navneet Gupta, Jukka Teittinen, Jesse Simonsson, Matthew J. Turnquist, Jonas Eriksson, Risto Anttila, Ohto Myllynen, Hannu Rämäkkö, Sofia Mäkikyrö, Lauri Koskinen:
A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan. 1-3
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