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ORCIDICCD 1998: Austin, Texas, USA
- International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA. IEEE Computer Society 1998, ISBN 0-8186-9099-2
- Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki:
A 690 ps read-access latency register file for a GHz integer microprocessor. 6-10 - Kevin J. Nowka
, Tibi Galambos:
Circuit design techniques for a gigahertz integer microprocessor. 11-16 - Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo:
Design methodology for a 1.0 GHz microprocessor. 17-23 - Irith Pomeranz, Sudhakar M. Reddy:
Improved built-in test pattern generators based on comparison units for synchronous sequential circuits. 26-31 - Chih-Ang Chen, Sandeep K. Gupta:
Efficient BIST TPG design and test set compaction for delay testing via input reduction. 32-39 - Hassan Ihs, Karim Arabi, Bozena Kaminska:
Testing digital to analog converters based on oscillation-test strategy using sigma-delta modulation. 40-46 - Alberto Allara, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto:
System-level performance estimation strategy for sw and hw. 48-53 - Suhrid A. Wadekar, Alice C. Parker:
Accuracy sensitive word-length selection for algorithm optimization. 54-61 - François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Imed Eddine Bennour:
Optimal design of synchronous circuits using software pipelining techniques. 62-67 - Qi Wang, Sarma B. K. Vrudhula:
On short circuit power estimation of CMOS inverters. 70-75 - Khalid Rahmat, José Neves, Jin-Fuw Lee:
Methods for calculating coupling noise in early design: a comparative analysis. 76-81 - Ashish Karandikar, Keshab K. Parhi:
Low power SRAM design using hierarchical divided bit-line approach. 82-88 - Richard E. Kessler, Edward J. McLellan, D. A. Webb:
The Alpha 21264 microprocessor architecture. 90-95 - Emily J. Shriver, Dale H. Hall, Nevine Nassif, Nadir E. Rahman, Nick L. Rethman, Gill Watt, Jim A. Farrell:
Timing verification of the 21264: A 600 MHz full-custom microprocessor. 96-103 - Mark Matson, Dan Bailey, Shane L. Bell, Larry L. Biro, Steve Butler, John Clouser, Jim Farrell, Mike Gowan, Donald A. Priore, Kathryn Wilcox:
Circuit implementation of a 600 MHz superscalar RISC microprocessor. 104-110 - Nathan Dohm, Carl Ramey, Darren Brown, Scot Hildebrandt, James Huggins, Michael Quinn, Scott A. Taylor:
Zen and the art of Alpha verification. 111-117 - Moises E. Robinson, Earl E. Swartzlander Jr.:
A reduction scheme to optimize the Wallace multiplier. 122-127 - Martin Kuhlmann, Keshab K. Parhi:
Fast low-power shared division and square-root architecture. 128-135 - Andreas Wassatsch, Steffen Dolling, Dirk Timmermann:
Area minimization of redundant CORDIC pipeline architectures. 136-141 - Peter-Michael Seidel, Guy Even:
How many logic levels does floating-point addition require? 142-149 - J. W. J. M. Rutten, Michel R. C. M. Berkelaar:
Efficient exact and heuristic minimization of hazard-free logic. 152-159 - Rajat Chaudhry, Tai-Hung Liu, Adnan Aziz, Jeffrey L. Burns:
Area-oriented synthesis for pass-transistor logic. 160-167 - Stan Grygiel, Marek A. Perkowski:
New compact representation of multiple-valued functions, relations, and non-deterministic state machines. 168-174 - Sumit Roy, Harm Arts, Prithviraj Banerjee:
A low-power logic optimization methodology based on a fast power-driven mapping. 175-181 - Seiji Takeuchi, Takayasu Sakurai:
A fine-grain, current mode scheme for VLSI proximity search engine. 184-185 - Carina Ben-Zvi, Patrick McGuinness, Franklin Lassandro:
An effective datapath design methodology for high-frequency design. 186-187 - Ran Ginosar, Rakefet Kol:
Adaptive synchronization. 188-189 - Rolf Hakenes, Yiannos Manoli:
The Microcore development system: a unified environment for designing new microprocessors. 190-191 - Viresh Paruthi, Nazanin Mansouri, Ranga Vemuri:
Automatic data path abstraction for verification of large scale designs. 192-194 - Jianping Lu, Sofiène Tahar, Dan Voicu, Xiaoyu Song:
Model checking of a real ATM switch. 195-198 - Wai-Kei Mak, D. F. Wong:
Performance-driven board-level routing for FPGA-based logic emulation. 199-201 - Maurice Kilavuka Inuani, Jonathan Saul:
Re-synthesis in technology mapping for heterogeneous FPGAs. 202-204 - Raju D. Venkataramana, N. Ranganathan:
A simple adaptive wormhole routing algorithm for MIMD systems. 205-207 - Afshin Ganjoo:
Branch assertion and elimination. 208-210 - Yun-Nan Chang, Keshab K. Parhi:
High-performance digit-serial complex-number multiplier-accumulator. 211-213 - Fatih Kocan, Daniel G. Saab:
Dynamic fault diagnosis for sequential circuits on reconfigurable hardware. 214-215 - Yu-Liang Wu, Hongbing Fan, C. K. Wong:
On thin Boolean functions and related optimum OBDD ordering. 216-218 - Natesan Venkateswaran, Dinesh Bhatia:
Clock-skew constrained placement for row based designs. 219-220 - Shen Hui Wu, Yashwant K. Malaiya, Anura P. Jayasumana:
Antirandom vs. pseudorandom testing. 221-223 - Simon Segars:
The ARM9 family-high performance microprocessors for embedded applications. 230-235 - Keith S. P. Clarke, Danny Kershaw:
The system design of a Windows CE ARM based micro-controller. 236-241 - T. Hopes:
Hardware/software co-verification, an IP vendors viewpoint. 242-246 - Stephen B. Furber, Jim D. Garside, D. A. Gilbert:
AMULET3: a high-performance self-timed ARM microprocessor. 247-252 - Dale E. Hoffman, Robert M. Averill III, Brian W. Curran, Yuen H. Chan, Allan H. Dansky, Robert F. Hatch, Timothy G. McNamara, Thomas J. McPherson, Gregory A. Northrop, Leon J. Sigal, Anthony Pelella, Patrick M. Williams:
Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor. 258-263 - Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa:
Comparative analysis of latches and flip-flops for high-performance systems. 264-269 - Ruchir Puri:
Design issues in mixed static-domino circuit implementations. 270-275 - Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji:
A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic. 276-281 - Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim:
A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics. 286-291 - Chichyang Chen, Chih-Huan Yang:
Pipelined computation of LNS addition/subtraction with very small lookup tables. 292-297 - Javier D. Bruguera, Tomás Lang:
Leading-one prediction scheme for latency improvement in single datapath floating-point adders. 298-305 - Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose:
An approach to verify a large scale system-on-a-chip using symbolic model checking. 308-313 - Nina Saxena, Jason Baumgartner, Avijit Saha, Jacob A. Abraham:
To model check or not to model check. 314-320 - Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
VEGA: a verification tool based on genetic algorithms. 321-326 - Jeffry T. Russell, Margarida F. Jacome:
Software power estimation and optimization for high performance, 32-bit embedded processors. 328-333 - Mohammad M. Mansour, Ayman I. Kayssi:
FPGA-based Internet Protocol Version 6 router. 334-339 - Karthikeya M. Gajjala Purna, Dinesh Bhatia:
Partitioning in time: a paradigm for reconfigurable computing. 340-345 - Luis A. Plana, Stephen H. Unger:
Pulse-mode macromodular systems. 348-353 - Fu-Chiung Cheng:
Practical design and performance evaluation of completion detection circuits. 354-359 - Simon W. Moore, Peter Robinson:
Rapid prototyping of self-timed circuits. 360-365 - Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson:
Evaluating the performance of active cache management schemes. 368-375 - Enyou Li, Clark D. Thomborson:
Data cache parameter measurements. 376-383 - Gul N. Khan:
Fault-tolerant architecture for high performance embedded system applications. 384-389 - Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri:
Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis. 392-399 - Miroslav N. Velev, Randal E. Bryant:
Incorporating timing constraints in the efficient memory model for symbolic ternary simulation. 400-406 - Yaun-Chung Hsu, Hsi-Chuan Chen, Shangzhi Sun, David Hung-Chang Du:
Timing analysis of combinational circuits containing complex gates. 407-412 - Tomás Lang, Enric Musoll, Jordi Cortadella:
Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus. 414-419 - Alberto Nannarelli, Tomás Lang:
Low-power radix-8 divider. 420-426 - Kenneth Y. Yun, Supratik Chakraborty, Kevin W. James, Robert H. Fairlie-Cuninghame, Rene L. Cruz:
A self-timed real-time sorting network. 427-434 - D. Corvino, Italo Epicoco, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto:
Automatic VHDL restructuring for RTL synthesis optimization and testability improvement. 436-441 - Victor J. Lam, Kunle Olukotun:
DCP: an algorithm for datapath/control partitioning of synthesizable RTL models. 442-449 - Smita Bakshi, Daniel D. Gajski:
Hierarchical pipelining for behaviors, loops, and operations. 450-455 - Nan Ni, Marius Pirvu, Laxmi N. Bhuyan:
Circular buffered switch design with wormhole routing and virtual channels. 466-473 - Andrew Chang, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Whay Sing Lee:
The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline. 474-481 - Paul Marriott, Ivan C. Kraljic, Yvon Savaria:
Parallel ultra large scale engine SIMD architecture for real-time digital signal processing applications. 482-487 - Kemal Ebcioglu, Jason Fritts, Stephen Kosonocky, Michael Gschwind, Erik R. Altman, Krishnan Kailas, Terry Bright:
An eight-issue tree-VLIW processor for dynamic binary translation. 488-495 - Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
On finding undetectable and redundant faults in synchronous sequential circuits. 498-503 - Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda, Roberto Vietti:
Enhancing topological ATPG with high-level information and symbolic techniques. 504-509 - Paulo F. Flores, Horácio C. Neto, João P. Marques Silva:
An exact solution to the minimum size test pattern problem. 510-515 - William E. Dougherty, R. D. (Shawn) Blanton:
Using regression analysis for GA-based ATPG parameter optimization. 516-521 - Joel Grodstein, Nick Rethman, Nevine Nassif:
Static race verification for networks with reconvergent clocks. 524-529 - Yaun-Chung Hsu, Shangzhi Sun, David Hung-Chang Du:
Finding the longest simple path in cyclic combinational circuits. 530-535 - Hoon Choi, Seung Ho Hwang:
Practical use of transition mode delay to solve the problems of floating mode delay under highly correlated input streams. 536-541 - Radj Radjassamy, Jo Dale Carothers:
A fractal compaction algorithm for efficient power estimation. 542-547 - J. John, Yin Teh, Francis Matus, Craig Chase:
Code coalescing unit: a mechanism to facilitate load store data communication. 550-557 - Lucian Codrescu, D. Scott Wills:
Profiling for input predictable threads. 558-565 - Ing-Jer Huang, Tzu-Chin Peng:
Analysis of ×86 instruction set usage for DOS/Windows applications and its implication on superscalar design. 566-573 - Jaime Velasco-Medina, Michael Nicolaidis:
Current-based testing for analog and mixed-signal circuits. 576-581 - Wei-Hsing Huang, Chin-Long Wey:
Test points selection process and diagnosability analysis of analog integrated circuits. 582-587 - Heebyung Yoon, Junwei Hou, Abhijit Chatterjee, Madhavan Swaminathan:
Fault detection and automated fault diagnosis for embedded integrated electrical passives. 588-593 - Ta-Cheng Lin, Sadiq M. Sait, Walling R. Cyre:
Buffer size driven partitioning for HW/SW co-design. 596-601 - Alex Doboli, Petru Eles:
Scheduling under data and control dependencies for heterogeneous architectures. 602-608 - Huiqun Liu, D. F. Wong:
Integrated partitioning and scheduling for hardware/software co-design. 609-614 - Aiguo Lu, Hans Eisenmann, Guenter Stenz, Frank M. Johannes:
Combining technology mapping with post-placement resynthesis for performance optimization. 616-621 - Lixin Su, Wray L. Buntine, A. Richard Newton, Bradley S. Peters:
Learning as applied to stochastic optimization for standard cell placement. 622-627 - Kai Zhu, Yao-Wen Chang, D. F. Wong:
Timing-driven routing for symmetrical-array-based FPGAs. 628-633 - Yiannos Manoli, W. Mokwa:
Silicon microsystems merging sensors, circuits and systems. 634-641
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