Quantization Strategy for Achieving Low-Cost, Accurate, Pareto-Optimal Convolutional Neural Networks Based on Analysis of Quantized Weight Parameters.

Fumihiko Tachibana

Kengo Nakata Daisuke Miyashita Asuka Maki Fumihiko Tachibana Shinichi Sasaki Jun Deguchi Ryuichi Fujimoto Quantization Strategy for Achieving Low-Cost, Accurate, Pareto-Optimal Convolutional Neural Networks Based on Analysis of Quantized Weight Parameters. 1526-1535 2025 108 IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 11 https://doi.org/10.1587/transfun.2025eap1034 db/journals/ieiceta/ieiceta108.html#NakataMMTSDF25 streams/journals/ieiceta

Fumihiko Tachibana Huy Cu Ngo Go Urakawa Takashi Toi Mitsuyuki Ashida Yuta Tsubouchi Mai Nozawa Junji Wadatsumi Hiroyuki Kobayashi Jun Deguchi A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver. 709-718 2024 107 IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 5 https://doi.org/10.1587/transfun.2023gcp0003 db/journals/ieiceta/ieiceta107.html#TachibanaNUTATNWKD24

Fumihiko Tachibana Huy Cu Ngo Go Urakawa Takashi Toi Mitsuyuki Ashida Yuta Tsubouchi Mai Nozawa Junji Wadatsumi Hiroyuki Kobayashi Jun Deguchi A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR. 505-508 2022 ESSCIRC https://doi.org/10.1109/ESSCIRC55480.2022.9911409 conf/esscirc/2022 db/conf/esscirc/esscirc2022.html#TachibanaNUTATN22 Kengo Nakata Daisuke Miyashita Asuka Maki Fumihiko Tachibana Shinichi Sasaki Jun Deguchi Ryuichi Fujimoto Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN. 1-4 2021 AICAS https://doi.org/10.1109/AICAS51828.2021.9458452 conf/aicas/2021 db/conf/aicas/aicas2021.html#NakataMMTSDF21

Asuka Maki Daisuke Miyashita Shinichi Sasaki Kengo Nakata Fumihiko Tachibana Tomoya Suzuki Jun Deguchi Ryuichi Fujimoto Weight Compression MAC Accelerator for Effective Inference of Deep Learning. 514-523 2020 103-C IEICE Trans. Electron. 10 https://doi.org/10.1587/transele.2019CTP0007 http://search.ieice.org/bin/summary.php?id=e103-c_10_514 db/journals/ieicetc/ieicetc103.html#MakiMSNTSDF20

Yuta Tsubouchi Daisuke Miyashita Takashi Toi Yuji Satoh Fumihiko Tachibana Junji Wadatsumi Makoto Morimoto Ryuichi Fujimoto Jun Deguchi A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems. 1086-1095 2019 54 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2018.2889704 https://www.wikidata.org/entity/Q128565432 db/journals/jssc/jssc54.html#TsubouchiMTSTWM19

Kengo Nakata Asuka Maki Daisuke Miyashita Fumihiko Tachibana Tomoya Suzuki Jun Deguchi Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision. 1 2019 ISCAS https://doi.org/10.1109/ISCAS.2019.8702208 conf/iscas/2019 db/conf/iscas/iscas2019.html#NakataMMTSD19 Asuka Maki Daisuke Miyashita Kengo Nakata Fumihiko Tachibana Tomoya Suzuki Jun Deguchi FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision. 47-50 2018 A-SSCC https://doi.org/10.1109/ASSCC.2018.8579342 conf/asscc/2018 db/conf/asscc/asscc2018.html#MakiMNTSD18 Yuta Tsubouchi Daisuke Miyashita Yuji Satoh Takashi Toi Fumihiko Tachibana Makoto Morimoto Junji Wadatsumi Jun Deguchi A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems. 149-150 2018 VLSI Circuits https://doi.org/10.1109/VLSIC.2018.8502340 conf/vlsic/2018 db/conf/vlsic/vlsic2018.html#TsubouchiMSTTMW18

Fumihiko Tachibana Osamu Hirabayashi Yasuhisa Takeyama Miyako Shizuno Atsushi Kawasumi Keiichi Kushida Azuma Suzuki Yusuke Niki Shinichi Sasaki Tomoaki Yabe Yasuo Unekawa A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. 320-321 2013 ISSCC https://doi.org/10.1109/ISSCC.2013.6487752 conf/isscc/2013 db/conf/isscc/isscc2013.html#TachibanaHTSKKSNSYU13 Jun Deguchi Fumihiko Tachibana Makoto Morimoto Masayoshi Chiba Takeshi Miyaba Hideki Tanaka Kyoichi Takenaka Satoshi Funayama Kunihiko Amano Kazuhide Sugiura Ryuta Okamoto Shouhei Kousai A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC. 494-495 2013 ISSCC https://doi.org/10.1109/ISSCC.2013.6487830 conf/isscc/2013 db/conf/isscc/isscc2013.html#DeguchiTMCMTTFASOK13 Atsushi Kawasumi Yasuhisa Takeyama Osamu Hirabayashi Keiichi Kushida Fumihiko Tachibana Yusuke Niki Shinichi Sasaki Tomoaki Yabe Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction. 1-4 2012 ICICDT https://doi.org/10.1109/ICICDT.2012.6232859 conf/icicdt/2012 db/conf/icicdt/icicdt2012.html#KawasumiTHKTNSY12 Atsushi Kawasumi Yasuhisa Takeyama Osamu Hirabayashi Keiichi Kushida Fumihiko Tachibana Yusuke Niki Shinichi Sasaki Tomoaki Yabe A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs. 100-101 2012 VLSIC https://doi.org/10.1109/VLSIC.2012.6243809 conf/vlsic/2012 db/conf/vlsic/vlsic2012.html#KawasumiTHKTNSY12

Yusuke Niki Atsushi Kawasumi Azuma Suzuki Yasuhisa Takeyama Osamu Hirabayashi Keiichi Kushida Fumihiko Tachibana Yuki Fujimura Tomoaki Yabe A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. 2545-2551 2011 46 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.2011.2164294 db/journals/jssc/jssc46.html#NikiKSTHKTFY11

Keiichi Kushida Osamu Hirabayashi Fumihiko Tachibana Hiroyuki Hara Atsushi Kawasumi Azuma Suzuki Yasuhisa Takeyama Yuki Fujimura Yusuke Niki Miyako Shizuno Shinichi Sasaki Tomoaki Yabe A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. 161-164 2011 A-SSCC https://doi.org/10.1109/ASSCC.2011.6123627 conf/asscc/2011 db/conf/asscc/asscc2011.html#KushidaHTHKSTFN11 Fumihiko Tachibana Hironori Sato Takahiro Yamashita Hiroyuki Hara Takeshi Kitahara Shuou Nomura Fumiyuki Yamane Yoshiro Tsuboi Keiko Seki Shuuji Matsumoto Yoshinori Watanabe Mototsugu Hamada A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. 29-32 2008 CICC https://doi.org/10.1109/CICC.2008.4672012 conf/cicc/2008 db/conf/cicc/cicc2008.html#TachibanaSYHKNYTSMWH08 Shuou Nomura Fumihiko Tachibana Tetsuya Fujita Chen Kong Teh Hiroyuki Usui Fumiyuki Yamane Yukimasa Miyamoto Chaiyasit Kumtornkittikul Hiroyuki Hara Takahiro Yamashita Jun Tanabe Masaru Uchiyama Yoshiro Tsuboi Takashi Miyamori Takeshi Kitahara Hironori Sato Y. Homma Shuuji Matsumoto Keiko Seki Y. Watanabe Mototsugu Hamada Makoto Takahashi A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. 262-263 2008 ISSCC https://doi.org/10.1109/ISSCC.2008.4523157 conf/isscc/2008 db/conf/isscc/isscc2008.html#NomuraTFTUYMKHYTUTMKSHMSWHT08 Kunihiko Amano Mitsuyuki Ashida Masayoshi Chiba Jun Deguchi Ryuichi Fujimoto Yuki Fujimura Tetsuya Fujita Satoshi Funayama Mototsugu Hamada Hiroyuki Hara Osamu Hirabayashi Y. Homma Atsushi Kawasumi Takeshi Kitahara Hiroyuki Kobayashi Shouhei Kousai Chaiyasit Kumtornkittikul Keiichi Kushida Asuka Maki Shuuji Matsumoto Takeshi Miyaba Takashi Miyamori Yukimasa Miyamoto Daisuke Miyashita Makoto Morimoto Kengo Nakata Huy Cu Ngo Yusuke Niki Shuou Nomura Mai Nozawa Ryuta Okamoto Shinichi Sasaki Hironori Sato Yuji Satoh Keiko Seki Miyako Shizuno Kazuhide Sugiura Azuma Suzuki Tomoya Suzuki Makoto Takahashi Kyoichi Takenaka Yasuhisa Takeyama Jun Tanabe Hideki Tanaka Chen Kong Teh Takashi Toi Yoshiro Tsuboi Yuta Tsubouchi Masaru Uchiyama Yasuo Unekawa Go Urakawa Hiroyuki Usui Junji Wadatsumi Y. Watanabe Yoshinori Watanabe Tomoaki Yabe Fumiyuki Yamane Takahiro Yamashita