{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,16]],"date-time":"2026-07-16T11:59:06Z","timestamp":1784203146845,"version":"3.55.0"},"reference-count":26,"publisher":"Institution of Engineering and Technology (IET)","issue":"6","license":[{"start":{"date-parts":[[2017,10,24]],"date-time":"2017-10-24T00:00:00Z","timestamp":1508803200000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"funder":[{"DOI":"10.13039\/501100008530","name":"European Regional Development Fund","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100008530","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["ietresearch.onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["IET Computers &amp; Digital Tech"],"published-print":{"date-parts":[[2017,11]]},"abstract":"<jats:p>\n                    Taking into consideration the requirements of real\u2010time embedded systems, the processor scheduler must guarantee a constant scheduling frequency, providing determinism and predictability of tasks execution. The purpose of this study is to implement the nMPRA (multi pipeline register architecture) processor into field\u2010programmable gate array, and to integrate the already existing scheduling methods, thus providing a preemptive schedulability analysis of the proposed architecture based on the pipeline assembly line and hardware scheduler. This study describes a hardware implementation of the real\u2010time scheduler named nHSE (hardware scheduler engine for\n                    <jats:italic>n<\/jats:italic>\n                    tasks) and presents the results obtained using the appropriate schedulability methods used in real\u2010time environments. The scheduling and task switch operations are the main source of non\u2010determinism, being successfully dealt with real\u2010time nMPRA concept, in order to improve the system's functionality. Some mechanisms used for synchronisation and inter\u2010task communication are also taken into consideration.\n                  <\/jats:p>","DOI":"10.1049\/iet-cdt.2017.0163","type":"journal-article","created":{"date-parts":[[2017,9,12]],"date-time":"2017-09-12T22:18:44Z","timestamp":1505254724000},"page":"221-230","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms"],"prefix":"10.1049","volume":"11","author":[{"given":"Ionel","family":"Zagan","sequence":"first","affiliation":[{"name":"Stefan cel Mare University of Suceava Suceava Romania"},{"name":"Integrated Center for Research, Development and Innovation in Advanced Materials, Nanotechnologies, and Distributed Systems for Fabrication and Control (MANSiD) Stefan cel Mare University Suceava Romania"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vasile Gheorghi\u0163\u0103","family":"G\u0103itan","sequence":"additional","affiliation":[{"name":"Stefan cel Mare University of Suceava Suceava Romania"},{"name":"Integrated Center for Research, Development and Innovation in Advanced Materials, Nanotechnologies, and Distributed Systems for Fabrication and Control (MANSiD) Stefan cel Mare University Suceava Romania"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"265","published-online":{"date-parts":[[2017,10,24]]},"reference":[{"key":"e_1_2_6_2_2","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4614-0676-1","volume-title":"Hard real\u2010time computing systems \u2013 predictable scheduling algorithms and applications","author":"Buttazzo G.C.","year":"2011"},{"key":"e_1_2_6_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2346542"},{"key":"e_1_2_6_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2012.2191754"},{"key":"e_1_2_6_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2013.2266081"},{"key":"e_1_2_6_6_2","doi-asserted-by":"crossref","unstructured":"Zimmer M. Broman D. Shaver C. et al.: \u2018FlexPRET: a processor platform for mixed\u2010criticality systems\u2019.Proc. of the 20th IEEE Real\u2010Time and Embedded Technology and Application Symp. (RTAS) Berlin Germany 15\u201317 April2014 doi:10.1109\/RTAS.2014.6925994","DOI":"10.1109\/RTAS.2014.6925994"},{"key":"e_1_2_6_7_2","unstructured":"MicroBlaze Soft Processor Core. Available atwww.xilinx.com\/products\/intellectual\u2010property\/microblazecore.html Xilinx accessed January 2017"},{"key":"e_1_2_6_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2009.2028359"},{"key":"e_1_2_6_9_2","doi-asserted-by":"crossref","unstructured":"T\u0103nase C.A.: \u2018An approach of MPRA technique over ARM cache architecture\u2019.2016 Int. Conf. on Development and Application Systems (DAS) Suceava Romania 2016 pp.86\u201390 doi:10.1109\/DAAS.2016.7492553","DOI":"10.1109\/DAAS.2016.7492553"},{"key":"e_1_2_6_10_2","unstructured":"Amber Open Source Project March 2015. Available athttp:\/\/opencores.org\/websvn filedetails?repname=amber&path=%2Famber%2Ftrunk%2Fdoc%2Famber\u2010core.pdf accessed November 2016"},{"key":"e_1_2_6_11_2","doi-asserted-by":"crossref","unstructured":"Baruah S.K.: \u2018The limited\u2010preemption uniprocessor scheduling of sporadic task systems\u2019.Proc. of the 17th Euromicro Conf. on Real\u2010Time Systems (ECRTS'05) Palma de Mallorca Balearic Islands Spain July2005 pp.137\u2013144 doi:10.1109\/ECRTS.2005.32","DOI":"10.1109\/ECRTS.2005.32"},{"key":"e_1_2_6_12_2","doi-asserted-by":"crossref","unstructured":"Yao G. Buttazzo G.C. Bertogna M.: \u2018Bounding the maximum length of non\u2010preemptive regions under fixed priority scheduling\u2019.Proc. of the 15th IEEE Int. Conf. on Embedded and Real\u2010Time Computing Systems and Applications (RTCSA'09) Beijing China August2009 pp.351\u2013360","DOI":"10.1109\/RTCSA.2009.44"},{"key":"e_1_2_6_13_2","first-page":"225","volume-title":"Advances in real\u2010time systems","author":"Burns A.","year":"1995"},{"key":"e_1_2_6_14_2","doi-asserted-by":"publisher","DOI":"10.4236\/jcc.2015.34005"},{"key":"e_1_2_6_15_2","doi-asserted-by":"crossref","unstructured":"Wang G. Guo H. Wang Y.: \u2018A novel heterogeneous scheduling algorithm with improved task priority\u2019.2015 IEEE 17th Int. Conf. on High Performance Computing and Communications 2015 IEEE 7th Int. Symp. on Cyberspace Safety and Security and 2015 IEEE 12th Int. Conf. on Embedded Software and Systems New York NY 2015 pp.1826\u20131831 doi:10.1109\/HPCC\u2010CSS\u2010ICESS.2015.48","DOI":"10.1109\/HPCC-CSS-ICESS.2015.48"},{"issue":"3","key":"e_1_2_6_16_2","first-page":"224","article-title":"A new round robin based scheduling algorithm for operating systems \u2013 dynamic quantum using the mean average","volume":"8","author":"Noon A.","year":"2011","journal-title":"Int. J. Comput. Sci. Issues (IJCSI)"},{"issue":"7","key":"e_1_2_6_17_2","first-page":"56","article-title":"A new method to improve round robin scheduling algorithm with quantum time based on harmonic\u2010arithmetic mean (HARM)","volume":"5","author":"Ale Agha A.E.","year":"2013","journal-title":"Int. J. Inf. Technol. Comput. Sci. (IJITCS)"},{"key":"e_1_2_6_18_2","first-page":"V4\u2010563","article-title":"The improved EDF scheduling algorithm for embedded real\u2010time system in the uncertain environment","volume":"4","author":"Xiaojie L.","year":"2010","journal-title":"2010 3rd Int. Conf. on Advanced Computer Theory and Engineering (ICACTE)"},{"key":"e_1_2_6_19_2","unstructured":"Ayers G.:\u2018eXtensible Utah Multicore (XUM) project at the University of Utah 2011\u20132012\u2019. Available athttp:\/\/opencores.org\/project mips32r1 accessed September 2015"},{"key":"e_1_2_6_20_2","unstructured":"Meakin B.: \u2018Multicore system design with Xum: the extensible Utah multicore project\u2019.Master of Science thesis The University of Utah May2010"},{"key":"e_1_2_6_21_2","volume-title":"Computer organization and design, the hardware\/software interface","author":"Patterson D.A.","year":"2011"},{"key":"e_1_2_6_22_2","unstructured":"MIPS\u00ae Architecture for Programmers Volume I\u2010A: Introduction to the MIPS32\u00ae Architecture Document Number: MD00082 Revision 3.02 21 March 2011 Available athttps:\/\/courses.engr.illinois.edu\/cs426\/Resources\/MIPS32INT\u2010AFP\u201003.02.pdf accessed May 2016"},{"key":"e_1_2_6_23_2","doi-asserted-by":"publisher","DOI":"10.1145\/202213.202217"},{"key":"e_1_2_6_24_2","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2016.0085"},{"key":"e_1_2_6_25_2","unstructured":"Kuacharoen P. Shalan M. Mooney V.J.III: \u2018A configurable hardware scheduler for real\u2010time systems\u2019.Proc. Engineering of Reconfigurable Systems and Algorithms 2003 pp.95\u2013101"},{"key":"e_1_2_6_26_2","volume-title":"Digital VLSI systems design: a design manual for implementation of projects on FPGAs and ASICs using Verilog","author":"Ramachandran S.","year":"2007"},{"key":"e_1_2_6_27_2","unstructured":"Ashenden P.J.: \u2018Digital design an embedded systems approach using Verilog\u2019 10 September 2007 ISBN: 978\u20100\u201012\u2010369527\u20107 eBook ISBN: 9780080553115"}],"container-title":["IET Computers &amp; Digital Techniques"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1049\/iet-cdt.2017.0163","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/full-xml\/10.1049\/iet-cdt.2017.0163","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/ietresearch.onlinelibrary.wiley.com\/doi\/pdf\/10.1049\/iet-cdt.2017.0163","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T06:18:33Z","timestamp":1761632313000},"score":1,"resource":{"primary":{"URL":"https:\/\/ietresearch.onlinelibrary.wiley.com\/doi\/10.1049\/iet-cdt.2017.0163"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,24]]},"references-count":26,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2017,11]]}},"alternative-id":["10.1049\/iet-cdt.2017.0163"],"URL":"https:\/\/doi.org\/10.1049\/iet-cdt.2017.0163","archive":["Portico"],"relation":{},"ISSN":["1751-8601"],"issn-type":[{"value":"1751-8601","type":"print"}],"subject":[],"published":{"date-parts":[[2017,10,24]]},"assertion":[{"value":"2017-07-26","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-08-23","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-10-24","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}