{"id":"https://openalex.org/W2097323086","doi":"https://doi.org/10.1109/isvlsi.2007.60","title":"Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan","display_name":"Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W2097323086","doi":"https://doi.org/10.1109/isvlsi.2007.60","mag":"2097323086"},"language":"en","primary_location":{"id":"doi:10.1109/isvlsi.2007.60","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2007.60","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100449770","display_name":"Zhipeng Liu","orcid":"https://orcid.org/0000-0002-5458-9362"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhipeng Liu","raw_affiliation_strings":["Department of Computer Science and Technology, Tsinghua University, Beijing, China","Dept-of Computer Science and Technology, Tsinghua University, Beijing,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Dept-of Computer Science and Technology, Tsinghua University, Beijing,","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034755987","display_name":"Jinian Bian","orcid":"https://orcid.org/0000-0002-4322-1503"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinian Bian","raw_affiliation_strings":["Department of Computer Science and Technology, Tsinghua University, Beijing, China","Dept-of Computer Science and Technology, Tsinghua University, Beijing,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Dept-of Computer Science and Technology, Tsinghua University, Beijing,","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101929507","display_name":"Qiang Zhou","orcid":"https://orcid.org/0000-0001-7369-3598"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Zhou","raw_affiliation_strings":["Department of Computer Science and Technology, Tsinghua University, Beijing, China","Dept-of Computer Science and Technology, Tsinghua University, Beijing,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Dept-of Computer Science and Technology, Tsinghua University, Beijing,","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101839097","display_name":"Hui Dai","orcid":"https://orcid.org/0000-0001-5024-559X"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hui Dai","raw_affiliation_strings":["Department of Computer Science and Technology, Tsinghua University, Beijing, China","Dept-of Computer Science and Technology, Tsinghua University, Beijing,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Dept-of Computer Science and Technology, Tsinghua University, Beijing,","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"279","last_page":"284"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9719516038894653},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7582696080207825},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5972477793693542},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5374966263771057},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4922727644443512},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4797695577144623},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.45785626769065857},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.43725740909576416},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.4254935681819916},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.4249194860458374},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37877029180526733},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3116645812988281},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25804197788238525},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.20999732613563538},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.1662059724330902},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08951583504676819},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.08467698097229004}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9719516038894653},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7582696080207825},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5972477793693542},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5374966263771057},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4922727644443512},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4797695577144623},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.45785626769065857},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.43725740909576416},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.4254935681819916},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.4249194860458374},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37877029180526733},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3116645812988281},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25804197788238525},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.20999732613563538},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.1662059724330902},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08951583504676819},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.08467698097229004},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isvlsi.2007.60","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isvlsi.2007.60","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1941899280","https://openalex.org/W1965585119","https://openalex.org/W2032444288","https://openalex.org/W2052031047","https://openalex.org/W2069162780","https://openalex.org/W2097099414","https://openalex.org/W2108904252","https://openalex.org/W2123455796","https://openalex.org/W2150282626","https://openalex.org/W2154907195","https://openalex.org/W2489328233","https://openalex.org/W2544147585","https://openalex.org/W4235923234","https://openalex.org/W4248183742","https://openalex.org/W4253343649","https://openalex.org/W6682184148","https://openalex.org/W6729594396"],"related_works":["https://openalex.org/W3141861494","https://openalex.org/W2781601456","https://openalex.org/W3010631755","https://openalex.org/W2080729117","https://openalex.org/W2115502122","https://openalex.org/W2138401961","https://openalex.org/W2353155791","https://openalex.org/W1987322154","https://openalex.org/W4253343649","https://openalex.org/W2032444288"],"abstract_inverted_index":{"This":[0],"article":[1],"proposes":[2],"an":[3],"efficient":[4],"algorithm":[5,79],"by":[6,101],"module":[7,70],"duplication":[8,24],"for":[9,62,67],"integration":[10],"of":[11,47,77],"high-level":[12,52],"synthesis":[13,53],"and":[14,21,41,54,92],"floorplan":[15,55],"to":[16,59,71],"optimize":[17],"the":[18,28,38,44,48,64,68,78,82,98],"interconnect":[19,29,39,90,95],"delay":[20,40],"power.":[22,42],"Module":[23],"can":[25],"bring":[26],"down":[27],"wire":[30],"length":[31],"among":[32],"physical":[33],"modules,":[34],"thereby":[35],"further":[36],"reducing":[37],"With":[43],"proper":[45],"generosity":[46],"area":[49],"constraint,":[50],"incremental":[51],"procedures":[56],"are":[57,87],"proposed":[58],"perform":[60],"iteratively":[61],"finding":[63],"best":[65],"place":[66],"duplicated":[69],"be":[72],"inserted.":[73],"The":[74],"key":[75],"contribution":[76],"lies":[80],"in":[81],"fact":[83],"that":[84],"our":[85],"designs":[86],"20.8%":[88],"more":[89,94],"delay-efficient":[91],"12.5%":[93],"power-efficient":[96],"over":[97],"results":[99],"produced":[100],"original":[102],"design":[103],"methods":[104]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
