Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.

S. Ramesh 0004 Shiva Ramesh 0004 LSI Logic Corporation, Milpitas, CA, USA S. Ramesh Ramesh S. S. Ramesh 0001 Indian Institute of Technology, Bombay, Mumbai, India https://www.cse.iitb.ac.in/~ramesh/ S. Ramesh 0002 Ramesh S. 0002 Sethu Ramesh General Motors R&D, India Science Lab, Bangalore, India https://orcid.org/0000-0002-8501-7447 https://www.wikidata.org/entity/Q130949701 S. Ramesh 0003 Ramesh Sekaran Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, India Malla Reddy Engineering College for Women, Secunderabad, India Anna University, Department of Information and Communication Engineering, Chennai, India https://orcid.org/0000-0002-6668-2142 https://orcid.org/0000-0002-6817-3878 https://www.wikidata.org/entity/Q87616222 https://www.scopus.com/authid/detail.uri?authorId=56601645600 S. Ramesh 0005 Ramesh Sundar Vignan Foundation for Science, Technology & Research, Guntur, India https://orcid.org/0000-0002-1369-3200 Shiva Ramesh R. Venkatraman R. Castagnetti Andres Teene Benjamin Mbouombouo S. Ramesh 0004 Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. 27-32 2009 ISQED https://doi.org/10.1109/ISQED.2009.4810265 https://doi.ieeecomputersociety.org/10.1109/ISQED.2009.4810265 conf/isqed/2009 db/conf/isqed/isqed2009.html#VenkatramanCTMR09 R. Venkatraman R. Castagnetti S. Ramesh 0004 The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. 190-195 2006 conf/isqed/2006 ISQED https://doi.org/10.1109/ISQED.2006.134 https://doi.ieeecomputersociety.org/10.1109/ISQED.2006.134 db/conf/isqed/isqed2006.html#VenkatramanCR06 Ruggero Castagnetti R. Venkatraman Brandon Bartz Carl Monzel T. Briscoe Andres Teene S. Ramesh 0004 A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. 193-196 2005 conf/isqed/2005 ISQED https://doi.org/10.1109/ISQED.2005.6 https://doi.ieeecomputersociety.org/10.1109/ISQED.2005.6 db/conf/isqed/isqed2005.html#CastagnettiVBMBTR05 Andres Teene Bob Davis Ruggero Castagnetti Jeff Brown S. Ramesh 0004 Impact of Interconnect Process Variations on Memory Performance and Design. 694-699 2005 conf/isqed/2005 ISQED https://doi.org/10.1109/ISQED.2005.63 https://doi.ieeecomputersociety.org/10.1109/ISQED.2005.63 db/conf/isqed/isqed2005.html#TeeneDCBR05 F. Duan R. Castagnetti R. Venkatraman O. Kobozeva S. Ramesh 0004 Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. 119-124 2003 conf/isqed/2003 ISQED https://doi.org/10.1109/ISQED.2003.1194719 https://doi.ieeecomputersociety.org/10.1109/ISQED.2003.1194719 db/conf/isqed/isqed2003.html#DuanCVKR03 Brandon Bartz T. Briscoe Jeff Brown R. Castagnetti Ruggero Castagnetti Bob Davis F. Duan O. Kobozeva Benjamin Mbouombouo Carl Monzel Andres Teene Ramakrishnan VenkatramanR. Venkatraman