<?xml version="1.0"?>
<dblpperson name="Maurizio Iacaruso" pid="205/3776" n="1">
<person key="homepages/205/3776" mdate="2017-09-05">
<author pid="205/3776">Maurizio Iacaruso</author>
</person>
<r><inproceedings key="conf/dsn/Chatzidimitriou17" mdate="2023-03-24">
<author pid="170/3249">Athanasios Chatzidimitriou</author>
<author pid="134/9991">Manolis Kaliorakis</author>
<author pid="79/1691">Dimitris Gizopoulos</author>
<author pid="205/3776">Maurizio Iacaruso</author>
<author pid="69/6111">Mauro Pipponzi</author>
<author pid="58/621">Riccardo Mariani</author>
<author orcid="0000-0002-7512-5356" pid="78/1169">Stefano Di Carlo</author>
<title>RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU.</title>
<pages>117-120</pages>
<year>2017</year>
<booktitle>DSN Workshops</booktitle>
<ee>https://doi.org/10.1109/DSN-W.2017.16</ee>
<ee>https://doi.ieeecomputersociety.org/10.1109/DSN-W.2017.16</ee>
<crossref>conf/dsn/2017w</crossref>
<url>db/conf/dsn/dsn2017w.html#Chatzidimitriou17</url>
</inproceedings>
</r>
<coauthors n="6" nc="1">
<co c="0"><na f="c/Carlo:Stefano_Di" pid="78/1169">Stefano Di Carlo</na></co>
<co c="0"><na f="c/Chatzidimitriou:Athanasios" pid="170/3249">Athanasios Chatzidimitriou</na></co>
<co c="0"><na f="g/Gizopoulos:Dimitris" pid="79/1691">Dimitris Gizopoulos</na></co>
<co c="0"><na f="k/Kaliorakis:Manolis" pid="134/9991">Manolis Kaliorakis</na></co>
<co c="0"><na f="m/Mariani:Riccardo" pid="58/621">Riccardo Mariani</na></co>
<co c="0"><na f="p/Pipponzi:Mauro" pid="69/6111">Mauro Pipponzi</na></co>
</coauthors>
</dblpperson>

