Diversity Methods for Improving Convergence and Accuracy of Quantum Error Correction Decoders Through Hardware Emulation.

Javier Valls-Coquillat Javier Valls Polytechnic University of Valencia, Spain https://orcid.org/0000-0002-9390-5022 https://www.wikidata.org/entity/Q90978817

Francisco Garcia-Herrero Javier Valls Llanos Vergara-Picazo Vicente Torres 0001 Diversity Methods for Improving Convergence and Accuracy of Quantum Error Correction Decoders Through Hardware Emulation. 2026 2071 10 Quantum https://doi.org/10.22331/q-2026-04-16-2071 db/journals/quantum/quantum10.html#GarciaHerreroVVT26 streams/journals/quantum

Gerardo José Ginovart-Panisello Ignasi Iriondo Tesa Panisello Monjo Silvia Riva Rodrigo Garcia Javier Valls Rosa Maria Alsina Pages Acoustic detection of the effects of prolonged fasting on newly hatched broiler chickens. 108763 2024 219 Comput. Electron. Agric. https://doi.org/10.1016/j.compag.2024.108763 db/journals/cea/cea219.html#GinovartPaniselloIMRGVP24

Julien du Crest Francisco Garcia-Herrero Mehdi Mhalla Valentin Savin Javier Valls Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes. 1334 2024 8 Quantum https://doi.org/10.22331/q-2024-05-02-1334 db/journals/quantum/quantum8.html#CrestGMSV24

Pau Salvador Ma José Canet Javier Valls Vicenç Almenar Juan Luis Corral Hybrid POF-VLC Network Downlink in Indoor Environments. 1-6 2024 VCC https://doi.org/10.1109/VCC63113.2024.10914348 conf/vcc/2024 db/conf/vcc/vcc2024.html#SalvadorCVAC24 streams/conf/vcc

Pau Salvador Vicenç Almenar Juan Luis Corral Javier Valls María José Canet Model and Methodology to Characterize Phosphor-Based White LED Visible Light Communication Links. 4637 2023 23 Sensors 10 https://doi.org/10.3390/s23104637 db/journals/sensors/sensors23.html#SalvadorACVC23

Julien du Crest Francisco Garcia-Herrero Mehdi Mhalla Valentin Savin Javier Valls Layered Decoding of Quantum LDPC Codes. 1-5 2023 ISTC https://doi.org/10.1109/ISTC57237.2023.10273477 conf/istc/2023 db/conf/istc/istc2023.html#CrestGMSV23

Javier Valls Francisco Garcia-Herrero Nithin Raveendran Bane Vasic Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes. 138734-138743 2021 9 IEEE Access https://doi.org/10.1109/ACCESS.2021.3118544 db/journals/access/access9.html#VallsGRV21

Gabriele Perrone Javier Valls Vicente Torres 0001 Francisco Garcia-Herrero Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems. 1793-1810 2019 38 Circuits Syst. Signal Process. 4 https://doi.org/10.1007/s00034-018-0938-x db/journals/cssp/cssp38.html#PerroneVTG19

J. M. Català-Pérez Jesus Omar Lacruz Francisco Garcia-Herrero Javier Valls David Declercq Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes. 5068-5080 2019 38 Circuits Syst. Signal Process. 11 https://doi.org/10.1007/s00034-019-01107-z https://www.wikidata.org/entity/Q128120451 db/journals/cssp/cssp38.html#Catala-PerezLGV19

Julián S. Bruno Vicenç Almenar Javier Valls FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems. 195-204 2019 64 Microprocess. Microsystems https://doi.org/10.1016/j.micpro.2018.12.002 https://www.wikidata.org/entity/Q128786985 db/journals/mam/mam64.html#BrunoAV19

Javier Valls Vicente Torres 0001 María José Canet Francisco Miguel Garcia-Herrero A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. 2198-2207 2019 66-I IEEE Trans. Circuits Syst. I Regul. Pap. 6 https://doi.org/10.1109/TCSI.2018.2882876 https://www.wikidata.org/entity/Q128749402 db/journals/tcas/tcasI66.html#VallsTCG19

Gabriele Perrone Javier Valls Vicente Torres 0001 Francisco Miguel Garcia-Herrero High-Throughput One-Channel RS(255, 239) Decoder. 110-114 2018 DSD https://doi.org/10.1109/DSD.2018.00032 https://doi.ieeecomputersociety.org/10.1109/DSD.2018.00032 conf/dsd/2018 db/conf/dsd/dsd2018.html#PerroneVTG18 Roberto Llorente Maria Morant Julián S. Bruno Vicenç Almenar Juan Luis Corral Jose M. Fuster Javier Valls Multidimensional Multiplexing in Multicore Fibre for Hybrid Optical Backhaul provision: The XCORE Approach. 1-4 2018 ICTON https://doi.org/10.1109/ICTON.2018.8473899 conf/icton/2018 db/conf/icton/icton2018.html#LlorenteMBACFV18 Vicente Torres 0001 Javier Valls María José Canet Francisco Garcia-Herrero Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239). 305-308 2018 NEWCAS https://doi.org/10.1109/NEWCAS.2018.8585684 conf/newcas/2018 db/conf/newcas/newcas2018.html#TorresVCG18

Vicente Torres 0001 Javier Valls Richard G. Lyons Fast- and Low-Complexity atan2(a, b) Approximation [Tips and Tricks]. 164-169 2017 34 IEEE Signal Process. Mag. 6 https://doi.org/10.1109/MSP.2017.2730898 db/journals/spm/spm34.html#TorresVL17

Vicente Torres 0001 Javier Valls A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number. 2663-2667 2017 25 IEEE Trans. Very Large Scale Integr. Syst. 9 https://doi.org/10.1109/TVLSI.2017.2700519 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2700519 db/journals/tvlsi/tvlsi25.html#TorresV17

Jesus Omar Lacruz Francisco Garcia-Herrero María José Canet Javier Valls High-Performance NB-LDPC Decoder With Reduction of Message Exchange. 1950-1961 2016 24 IEEE Trans. Very Large Scale Integr. Syst. 5 https://doi.org/10.1109/TVLSI.2015.2493041 db/journals/tvlsi/tvlsi24.html#LacruzGCV16

Jesus Omar Lacruz Francisco Garcia-Herrero María José Canet Javier Valls Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm. 2643-2653 2016 24 IEEE Trans. Very Large Scale Integr. Syst. 8 https://doi.org/10.1109/TVLSI.2016.2514484 db/journals/tvlsi/tvlsi24.html#LacruzGCV16a

Julián S. Bruno Vicenç Almenar Javier Valls Juan L. Corral Low-Complexity Time Synchronization Algorithm for Optical OFDM PON System Using a Directly Modulated DFB Laser. 1025-1033 2015 7 JOCN 11 https://doi.org/10.1364/jocn.7.001025 db/journals/jocnet/jocnet7.html#BrunoAVC15

Jesus Omar Lacruz Francisco Garcia-Herrero Javier Valls-Coquillat David Declercq One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes. 177-184 2015 62-I IEEE Trans. Circuits Syst. I Regul. Pap. 1 https://doi.org/10.1109/TCSI.2014.2354753 db/journals/tcas/tcasI62.html#LacruzGVD15

Jesus Omar Lacruz Francisco Garcia-Herrero David Declercq Javier Valls Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes. 1783-1792 2015 23 IEEE Trans. Very Large Scale Integr. Syst. 9 https://doi.org/10.1109/TVLSI.2014.2344113 db/journals/tvlsi/tvlsi23.html#LacruzGDV15

Jesus Omar Lacruz Francisco Garcia-Herrero Javier Valls Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages. 2676-2679 2015 23 IEEE Trans. Very Large Scale Integr. Syst. 11 https://doi.org/10.1109/TVLSI.2014.2377194 db/journals/tvlsi/tvlsi23.html#LacruzGV15

Jesus Omar Lacruz Francisco Garcia-Herrero Ma José Canet Javier Valls Asuncion Perez-Pascual A 630 Mbps non-binary LDPC decoder for FPGA. 1989-1992 2015 ISCAS https://doi.org/10.1109/ISCAS.2015.7169065 conf/iscas/2015 db/conf/iscas/iscas2015.html#LacruzGCVP15

Francisco Garcia-Herrero David Declercq Javier Valls Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes. 749-752 2014 18 IEEE Commun. Lett. 5 https://doi.org/10.1109/LCOMM.2014.030914.132867 db/journals/icl/icl18.html#Garcia-HerreroDV14

J. M. Català-Pérez Francisco Garcia-Herrero Javier Valls K. Liu Shu Lin 0001 Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree. 2065-2068 2014 18 IEEE Commun. Lett. 12 https://doi.org/10.1109/LCOMM.2014.2363112 db/journals/icl/icl18.html#Catala-PerezGVLL14

Guillermo A. Jaquenod Javier Valls Javier Siman Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. 2014 2014 Int. J. Reconfigurable Comput. https://doi.org/10.1155/2014/546264 https://www.wikidata.org/entity/Q59046541 db/journals/ijrc/ijrc2014.html#JaquenodVS14 546264:1-546264:5

Fabian Angarita Javier Valls Vicenç Almenar Vicente Torres-Carot Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor. 2150-2158 2014 61-I IEEE Trans. Circuits Syst. I Regul. Pap. 7 https://doi.org/10.1109/TCSI.2014.2304660 db/journals/tcas/tcasI61.html#AngaritaVAT14

Francisco Garcia-Herrero María José Canet Javier Valls Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm. 1455-1459 2014 22 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/TVLSI.2013.2276067 db/journals/tvlsi/tvlsi22.html#Garcia-HerreroCV14

Francisco Garcia-Herrero Erbao Li David Declercq Javier Valls Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes. 2256-2267 2014 22 IEEE Trans. Very Large Scale Integr. Syst. 11 https://doi.org/10.1109/TVLSI.2013.2292900 db/journals/tvlsi/tvlsi22.html#Garcia-HerreroLDV14

Francisco Garcia-Herrero David Declercq Javier Valls A symbol flipping decoder for NB-LDPC relying on multiple votes. 203-207 2014 ISTC https://doi.org/10.1109/ISTC.2014.6955114 conf/istc/2014 db/conf/istc/istc2014.html#Garcia-HerreroD14

Francisco Garcia-Herrero María José Canet Javier Valls Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes. 727-741 2013 32 Circuits Syst. Signal Process. 2 https://doi.org/10.1007/s00034-012-9481-3 db/journals/cssp/cssp32.html#Garcia-HerreroC13

Erbao Li Francisco Garcia-Herrero David Declercq Kiran K. Gunnam Jesus Omar Lacruz Javier Valls Low latency T-EMS decoder for non-binary LDPC codes. 831-835 2013 ACSSC https://doi.org/10.1109/ACSSC.2013.6810404 conf/acssc/2013 db/conf/acssc/acssc2013.html#LiGDGLV13 Francisco Garcia-Herrero Ma José Canet Javier Valls High-speed NB-LDPC decoder for wireless applications. 215-220 2013 ISPACS https://doi.org/10.1109/ISPACS.2013.6704549 conf/ispacs/2013 db/conf/ispacs/ispacs2013.html#Garcia-HerreroCV13

Francisco Garcia-Herrero María José Canet Javier Valls Mark F. Flanagan Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes. 909-912 2012 16 IEEE Commun. Lett. 6 https://doi.org/10.1109/LCOMM.2012.040912.120423 db/journals/icl/icl16.html#Garcia-HerreroCVF12

Fabian Angarita José Marín-Roig Vicenç Almenar Javier Valls Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation. 2575-2581 2012 6 IET Commun. 16 https://doi.org/10.1049/iet-com.2011.0542 db/journals/iet-com/iet-com6.html#AngaritaMAV12

María José Canet Javier Valls Vicenç Almenar José Marín-Roig FPGA implementation of an OFDM-based WLAN receiver. 232-244 2012 36 Microprocess. Microsystems 3 https://doi.org/10.1016/j.micpro.2011.11.004 db/journals/mam/mam36.html#CanetVAM12

Roberto Gutiérrez Vicente Torres-Carot Javier Valls Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method. 501-505 2012 59-II IEEE Trans. Circuits Syst. II Express Briefs 8 https://doi.org/10.1109/TCSII.2012.2204119 db/journals/tcas/tcasII59.html#GutierrezTV12

Francisco Garcia-Herrero María José Canet Javier Valls Pramod Kumar Meher High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. 568-573 2012 20 IEEE Trans. Very Large Scale Integr. Syst. 3 https://doi.org/10.1109/TVLSI.2010.2103961 db/journals/tvlsi/tvlsi20.html#Garcia-HerreroCVM12

Fabian Angarita Trinidad Sansaloni María José Canet Javier Valls Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes. 99-104 2012 66 J. Signal Process. Syst. 2 https://doi.org/10.1007/s11265-011-0580-3 db/journals/vlsisp/vlsisp66.html#AngaritaSCV12

Fabian Angarita Trinidad Sansaloni Asuncion Perez-Pascual Javier Valls Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes. 139-149 2012 68 J. Signal Process. Syst. 2 https://doi.org/10.1007/s11265-011-0592-z db/journals/vlsisp/vlsisp68.html#AngaritaSPV12

María José Canet Vicenc Almenar-Terre Santiago J. Flores Javier Valls Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles. 287-301 2012 68 J. Signal Process. Syst. 3 https://doi.org/10.1007/s11265-011-0618-6 db/journals/vlsisp/vlsisp68.html#CanetAFV12

Fabian Angarita Vicente Torres-Carot Asuncion Perez-Pascual Javier Valls High-throughput FPGA-based emulator for structured LDPC codes. 404-407 2012 ICECS https://doi.org/10.1109/ICECS.2012.6463664 conf/icecsys/2012 db/conf/icecsys/icecsys2012.html#AngaritaTPV12 Vicente Torres-Carot Asuncion Perez-Pascual Trinidad Sansaloni Javier Valls Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA. 408-411 2012 ICECS https://doi.org/10.1109/ICECS.2012.6463663 conf/icecsys/2012 db/conf/icecsys/icecsys2012.html#Torres-CarotPSV12 Francisco Garcia-Herrero María José Canet Javier Valls Decoder for an enhanced serial generalized bit flipping algorithm. 412-415 2012 ICECS https://doi.org/10.1109/ICECS.2012.6463662 conf/icecsys/2012 db/conf/icecsys/icecsys2012.html#Garcia-HerreroCV12

Francisco Garcia-Herrero Javier Valls Pramod Kumar Meher High-Speed RS(255, 239) Decoder Based on LCC Decoding. 1643-1669 2011 30 Circuits Syst. Signal Process. 6 https://doi.org/10.1007/s00034-011-9327-4 db/journals/cssp/cssp30.html#Garcia-HerreroV11

Roberto Gutiérrez Javier Valls Low Cost Hardware Implementation of Logarithm Approximation. 2326-2330 2011 19 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2010.2081387 db/journals/tvlsi/tvlsi19.html#GutierrezV11

Roberto Gutiérrez Vicente Torres-Carot Javier Valls-Coquillat FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques. 588-596 2010 56 J. Syst. Archit. 11 https://doi.org/10.1016/j.sysarc.2010.07.013 db/journals/jsa/jsa56.html#GutierrezTV10

Fabian Angarita Ma José Canet Trinidad Sansaloni Vicenç Almenar Javier Valls Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN. 1333-1337 2009 18 J. Circuits Syst. Comput. 7 https://doi.org/10.1142/S0218126609005691 db/journals/jcsc/jcsc18.html#AngaritaCSAV09

Pramod Kumar Meher Javier Valls Tso-Bing Juang K. Sridharan 0001 Koushik Maharatna 50 Years of CORDIC: Algorithms, Architectures, and Applications. 1893-1907 2009 56-I IEEE Trans. Circuits Syst. I Regul. Pap. 9 https://doi.org/10.1109/TCSI.2009.2025803 https://www.wikidata.org/entity/Q64387156 db/journals/tcas/tcasI56.html#MeherVJSM09

Vicente Torres-Carot A. Perez-Pascual T. Sansaloni Javier Valls Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. 17-23 2009 56 J. Signal Process. Syst. 1 https://doi.org/10.1007/s11265-008-0252-0 db/journals/vlsisp/vlsisp56.html#TorresPSV09

Roberto Gutiérrez Javier Valls Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications. 25-33 2009 56 J. Signal Process. Syst. 1 https://doi.org/10.1007/s11265-008-0253-z db/journals/vlsisp/vlsisp56.html#GutierrezV09

A. Perez-Pascual T. Sansaloni Vicente Torres-Carot Vicenc Almenar-Terre Javier Valls Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems. 35-40 2009 56 J. Signal Process. Syst. 1 https://doi.org/10.1007/s11265-008-0254-y db/journals/vlsisp/vlsisp56.html#Perez-PascualSTAV09

Roberto Gutiérrez Javier Valls Asuncion Perez-Pascual FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic. 609-612 2009 FPL https://doi.org/10.1109/FPL.2009.5272379 conf/fpl/2009 db/conf/fpl/fpl2009.html#GutierrezVP09

Fabian Angarita Ma José Canet T. Sansaloni Javier Valls Vicenc Almenar-Terre Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. 35-44 2008 52 J. Signal Process. Syst. 1 https://doi.org/10.1007/s11265-007-0071-8 https://www.wikidata.org/entity/Q56940748 db/journals/vlsisp/vlsisp52.html#AngaritaCSVA08

Fabian Angarita Ma José Canet T. Sansaloni A. Perez-Pascual Javier Valls Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. 181-191 2008 52 J. Signal Process. Syst. 2 https://doi.org/10.1007/s11265-007-0146-6 db/journals/vlsisp/vlsisp52.html#AngaritaCSPV08

José Marín-Roig Vicenç Almenar Javier Valls Ma José Canet 64-QAM 4×4 MIMO decoders based on Successive Projection Algorithm. 610-613 2008 ICECS https://doi.org/10.1109/ICECS.2008.4674927 conf/icecsys/2008 db/conf/icecsys/icecsys2008.html#Marin-RoigAVC08

Trinidad Sansaloni Asuncion Perez-Pascual Vicente Torres-Carot Vicenç Almenar José F. Toledo Javier Valls FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices. 229-235 2007 50 IEEE Trans. Educ. 3 https://doi.org/10.1109/TE.2007.900025 db/journals/te/te50.html#SansaloniPTATV07

T. Sansaloni A. Perez-Pascual Vicente Torres-Carot Javier Valls Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. 183-187 2007 47 J. VLSI Signal Process. 2 https://doi.org/10.1007/s11265-007-0055-8 db/journals/vlsisp/vlsisp47.html#SansaloniPTV07

A. Perez-Pascual T. Sansaloni Vicente Torres 0001 Vicenç Almenar Javier Valls Design of an efficient digital down-converter for a SDR-based DVB-S receiver. 256-259 2007 ECCTD https://doi.org/10.1109/ECCTD.2007.4529585 conf/ecctd/2007 db/conf/ecctd/ecctd2007.html#Perez-PascualST07 Ma José Canet Vicenç Almenar Santiago J. Flores Javier Valls Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard. 560-564 2007 EUSIPCO https://ieeexplore.ieee.org/document/7098866/ conf/eusipco/2007 db/conf/eusipco/eusipco2007.html#CanetAFV07 Roberto Gutiérrez Javier Valls Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms. 472-475 2007 FPL https://doi.org/10.1109/FPL.2007.4380692 conf/fpl/2007 db/conf/fpl/fpl2007.html#GutierrezV07 Fabian Angarita Preciado María José Canet Trinidad Sansaloni Balaguer Vicenc Almenar-Terre Javier Valls-Coquillat Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN. 586-588 2007 ICECS https://doi.org/10.1109/ICECS.2007.4511059 conf/icecsys/2007 db/conf/icecsys/icecsys2007.html#PreciadoCBAC07 María José Canet Vicenç Almenar José Marín-Roig Javier Valls Time Synchronization for the IEEE 802.11a/g WLAN Standard. 1-5 2007 PIMRC https://doi.org/10.1109/PIMRC.2007.4394066 conf/pimrc/2007 db/conf/pimrc/pimrc2007.html#CanetAMV07

Javier Valls Trinidad Sansaloni Asuncion Perez-Pascual Vicente Torres 0001 Vicenç Almenar The use of CORDIC in software defined radios: a tutorial. 46-50 2006 44 IEEE Commun. Mag. 9 https://doi.org/10.1109/MCOM.2006.1705978 https://www.wikidata.org/entity/Q111898632 db/journals/cm/cm44.html#VallsSPTA06

Vicente Torres-Carot A. Perez-Pascual T. Sansaloni Javier Valls Design of high performance timing recovery loops for communication applications. 1-4 2006 SiPS https://doi.org/10.1109/SIPS.2006.352545 conf/sips/2006 db/conf/sips/sips2006.html#TorresPSV06 Ma José Canet Ian J. Wassell Javier Valls Vicenç Almenar Performance evaluation of fine time synchronizers for WLANs. 1-4 2005 EUSIPCO https://ieeexplore.ieee.org/document/7078062/ conf/eusipco/2005 db/conf/eusipco/eusipco2005.html#CanetWVA05 Elias Todorovich Fabian Angarita Javier Valls Eduardo I. Boemo Statistical Power Estimation for FPGA. 515-518 2005 conf/fpl/2005 FPL db/conf/fpl/fpl2005.html#TodorovichAVB05 https://doi.org/10.1109/FPL.2005.1515774 https://doi.ieeecomputersociety.org/10.1109/FPL.2005.1515774 Fabian Angarita A. Perez-Pascual T. Sansaloni Javier Valls Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. 535-538 2005 conf/fpl/2005 FPL db/conf/fpl/fpl2005.html#AngaritaPSV05 https://doi.org/10.1109/FPL.2005.1515779 https://doi.ieeecomputersociety.org/10.1109/FPL.2005.1515779 Elias Todorovich Eduardo I. Boemo Francisco Cardells-Tormo Javier Valls Power analysis and estimation tool integrated with XPOWER. 259 2004 conf/fpga/2004 FPGA https://doi.org/10.1145/968280.968356 db/conf/fpga/fpga2004.html#TodorovichBCV04 Ma José Canet Felip Vicedo Vicenc Almenar-Terre Javier Valls-Coquillat Eduardo R. de Lima Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. 494-504 https://doi.org/10.1007/978-3-540-30117-2_51 2004 conf/fpl/2004 FPL db/conf/fpl/fpl2004.html#CanetVAVL04 Ma José Canet Felip Vicedo Vicenç Almenar Javier Valls Eduardo R. de Lima A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. 531-535 2004 PIMRC https://doi.org/10.1109/PIMRC.2004.1370927 conf/pimrc/2004 db/conf/pimrc/pimrc2004.html#CanetVAVL04

Francisco Cardells-Tormo Javier Valls-Coquillat Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs. 135-138 2003 50 IEEE Trans. Circuits Syst. II Express Briefs 3 https://doi.org/10.1109/TCSII.2003.809716 db/journals/tcasII/tcasII50.html#Cardells-TormoV03

Javier Valls Eduardo I. Boemo Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers. 317-322 2003 50 IEEE Trans. Circuits Syst. II Express Briefs 6 https://doi.org/10.1109/TCSII.2003.811438 db/journals/tcasII/tcasII50.html#VallsB03

T. Sansaloni Javier Valls Keshab K. Parhi Digit-Serial Complex-Number Multipliers on FPGAs. 105-115 2003 33 J. VLSI Signal Process. 1-2 https://doi.org/10.1023/A:1021197903170 db/journals/vlsisp/vlsisp33.html#SansaloniVP03

Francisco Cardells-Tormo Javier Valls-Coquillat Vicenc Almenar-Terre Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S. 31-40 https://doi.org/10.1007/978-3-540-45234-8_4 2003 conf/fpl/2003 FPL db/conf/fpl/fpl2003.html#Cardells-TormoVA03 José Marín-Roig Vicente Torres-Carot Ma José Canet Asuncion Perez-Pascual Trinidad Sansaloni Francisco Cardells-Tormo Fabian Angarita Felip Vicedo Vicenc Almenar-Terre Javier Valls-Coquillat DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. 988-991 https://doi.org/10.1007/978-3-540-45234-8_102 2003 conf/fpl/2003 FPL db/conf/fpl/fpl2003.html#Mari-RoigTCPSCAVAV03 Francisco Cardells-Tormo Javier Valls-Coquillat Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs. 260-263 2003 conf/iscas/2003 ISCAS (2) https://doi.org/10.1109/ISCAS.2003.1205955 db/conf/iscas/iscas2003-2.html#Cardells-TormoV03

Javier Valls Martin Kuhlmann Keshab K. Parhi Evaluation of CORDIC Algorithms for FPGA Design. 207-222 2002 32 J. VLSI Signal Process. 3 https://doi.org/10.1023/A:1020205217934 db/journals/vlsisp/vlsisp32.html#VallsKP02

Francisco Cardells-Tormo Javier Valls-Coquillat Vicenc Almenar-Terre Vicente Torres-Carot Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard. 102-111 2002 conf/fpl/2002 FPL https://doi.org/10.1007/3-540-46117-5_12 db/conf/fpl/fpl2002.html#Cardells-TormoVAT02 Francisco Cardells-Tormo Javier Valls-Coquillat High Performance Quadrature Digital Mixers for FPGAs. 905-914 2002 conf/fpl/2002 FPL https://doi.org/10.1007/3-540-46117-5_93 db/conf/fpl/fpl2002.html#Cardells-TormoV02 A. Perez-Pascual T. Sansaloni Javier Valls FPGA-based radix-4 butterflies for HIPERLAN/2. 277-280 2002 conf/iscas/2002 ISCAS (3) https://doi.org/10.1109/ISCAS.2002.1010214 db/conf/iscas/iscas2002-3.html#Perez-PascualSV02 T. Sansaloni A. Perez-Pascual Javier Valls Distributed arithmetic radix-2 butterflies for FPGA. 521-524 2001 ICECS https://doi.org/10.1109/ICECS.2001.957793 conf/icecsys/2001 db/conf/icecsys/icecsys2001.html#SansaloniPV01 A. Perez-Pascual T. Sansaloni Javier Valls FPGA based on-line complex-number multipliers. 1481-1484 2001 ICECS https://doi.org/10.1109/ICECS.2001.957495 conf/icecsys/2001 db/conf/icecsys/icecsys2001.html#Perez-PascualSV01 Trinidad Sansaloni Javier Valls Keshab K. Parhi FPGA-based digit-serial complex number multiplier-accumulator. 585-588 2000 ISCAS https://doi.org/10.1109/ISCAS.2000.858819 conf/iscas/2000 db/conf/iscas/iscas2000.html#SansaloniVP00 Marcos Martínez-Peiró Javier Valls T. Sansaloni A. Perez-Pascual Eduardo I. Boemo A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation. 241-244 1999 ICECS https://doi.org/10.1109/ICECS.1999.812268 conf/icecsys/1999 db/conf/icecsys/icecsys1999.html#Martinez-PeiroV99 A. Perez-Pascual Javier Valls Marcos M. Peiró Efficient complex-number multipliers mapped on FPGA. 1123-1126 1999 ICECS https://doi.org/10.1109/ICECS.1999.813431 conf/icecsys/1999 db/conf/icecsys/icecsys1999.html#Perez-PascualVP99 Javier Valls Trini Sansaloni Marcos Martínez-Peiró Eduardo I. Boemo Fast FPGA-based pipelined digit-serial/parallel multipliers. 482-485 1999 conf/iscas/1999 ISCAS (1) https://doi.org/10.1109/ISCAS.1999.777931 db/conf/iscas/iscas1999-1.html#VallsSPB99 Javier Valls Marcos M. Peiró Trinidad Sansaloni Eduardo I. Boemo Design and FPGA implementation of digit-serial FIR filters. 191-194 1998 ICECS https://doi.org/10.1109/ICECS.1998.814860 conf/icecsys/1998 db/conf/icecsys/icecsys1998.html#VallsPSB98 Vicenc Almenar-TerreVicenç Almenar Fabian AngaritaFabian Angarita Preciado Eduardo I. Boemo Julián S. Bruno Ma José CanetMaría José Canet Fran CardellsFrancisco Cardells-Tormo J. M. Català-Pérez Juan L. CorralJuan Luis Corral Julien du Crest David Declercq Mark F. Flanagan Santiago J. Flores Jose M. Fuster Rodrigo Garcia Francisco Garcia-HerreroFrancisco Miguel Garcia-Herrero Gerardo José Ginovart-Panisello Kiran K. Gunnam Roberto Gutiérrez Ignasi Iriondo Guillermo A. Jaquenod Tso-Bing Juang Martin Kuhlmann Jesus Omar Lacruz Erbao Li Eduardo R. de Lima Shu Lin 0001 K. Liu Roberto Llorente Richard G. Lyons Koushik Maharatna José Marín-Roig Marcos Martínez-Peiró Pramod Kumar Meher Mehdi Mhalla Tesa Panisello Monjo Maria Morant Rosa Maria Alsina Pages Keshab K. Parhi Marcos M. Peiró Asuncion Perez-PascualA. Perez-Pascual Gabriele Perrone Nithin Raveendran Silvia Riva Pau Salvador T. SansaloniTrinidad SansaloniTrinidad Sansaloni Balaguer Trini Sansaloni Valentin Savin Javier Siman K. Sridharan 0001 Elias Todorovich José F. Toledo Vicente Torres 0001Vicente Torres-Carot Bane Vasic Llanos Vergara-Picazo Felip Vicedo Ian J. Wassell