A 7F<sup>2</sup> cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.

Heinz Hoenigschmid Alexander Frey John K. DeBrosse Toshiaki Kirihata Gerhard Mueller Daniel W. Storaska Gabriel Daniel Gerd Frankowsky Kevin P. Guay David R. Hanson Louis Lu-Chen Hsu Brian Ji Dmitry G. Netis Steve Panaroni Carl Radens Armin M. Reith Hartmud Terletzki Oliver Weinfurtner Johann Alsmeier Werner Weber Matthew R. Wordeman A 7F<sup>2</sup> cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. 713-718 2000 35 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/4.841498 db/journals/jssc/jssc35.html#HoenigschmidFDK00