Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps.

Preetam Tadeparthy M. Das Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps. 581-584 2002 conf/iscas/2002 ISCAS (5) https://doi.org/10.1109/ISCAS.2002.1010770 db/conf/iscas/iscas2002-5.html#TadeparthyD02