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<dblp>
<article key="journals/jssc/KimPSKKSPC25" mdate="2025-08-09">
<author orcid="0009-0005-1270-8051">Jihee Kim</author>
<author orcid="0009-0002-5229-3418">Jia Park</author>
<author orcid="0000-0001-9758-2980">Jiwon Shin</author>
<author orcid="0009-0007-4260-0556">Hanseok Kim</author>
<author>Kahyun Kim</author>
<author>Haengbeom Shin</author>
<author orcid="0009-0000-1883-3826">Ha-Jung Park</author>
<author orcid="0000-0002-3556-8689">Woo-Seok Choi</author>
<title>A 4 &#215; 32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR With Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution.</title>
<pages>2751-2764</pages>
<year>2025</year>
<month>August</month>
<volume>60</volume>
<journal>IEEE J. Solid State Circuits</journal>
<number>8</number>
<ee>https://doi.org/10.1109/JSSC.2025.3532963</ee>
<url>db/journals/jssc/jssc60.html#KimPSKKSPC25</url>
<stream>streams/journals/jssc</stream>
</article>
</dblp>
