Abstract
Early power estimation in current designflows becomes more important nowadays. To meet this need, power estimation even on the algorithmic level has become an important step in the typical design flow. This helps the designer to choose the right algorithm right from the start and much optimisation potential can be used due to the focus on the crucial parts. In particular, algorithms for digital signal processing as applied in mobile communication systems are very power sensitive. Such algorithms massively contain multiplications with constants on parts of digital filters. In this paper we propose on the one hand our new decomposition algorithm for (nearly) optimal synthesis of constant coefficient multipliers which we use for the evaluation of our new power model. On the other hand we propose a new power model based on the canonical signed digit (CSD) approach which can be used very fast and where the deviation of the power compared to the time consuming decomposition is 4.9%.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Booth, D.: A signed binary multiplication technique. Quart. J. Mech. App. Math. IV(2), 236–240 (1951)
Reitwiesner, G.W.: ‘“Binary Arithmetic’”. Advances in Computers 1, 231–308 (1960)
Hartley, R.I.: Subexpression Sharing in Filters Using Canonical Signed Digit Multipliers. IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing 43, 677–688 (1996)
Stammermann, A., Helms, D., Schulte, M., Schulz, A., Nebel, W.: Binding, Allocation and Floorplanning in Low Power High-Level Synthesis. In: International Conference on Computer Aided Design, ICCAD (2003)
Potkonjak, M., Srivastava, M.B., Chandrakasan, A.P.: Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elemination. IEEE Transactions CAD 15, 151–165 (1996)
Paško, R., Schaumont, P., Derudder, V., Vernalde, S., Ďuracková, D.: A new algorithm for elimination of common subexpressions. IEEE Transactions CAD 18, 58–68 (1999)
Martínez-Peiró, M., Boemo, E.I., Wahammar, L.: Design of highspeed multiplierless filters using a nonrecursive signed common subexpression algorithm. IEEE Transactions on Circuits and Systems-II 49, 196–203 (2002)
Bull, D.R., Horrcks, D.H.: Primitive operator digital filter. In: Proceedings Inst. Elect. Eng. Circuits Devices Syst., vol. 138, pp. 401–412 (1991)
Dempster, G., Macleod, M.D.: Use of minimum adder multiplier blocks in FIR digital filters. IEEE Transactions on Circuits and Systems-II 42, 569–577 (1995)
Kang, H.-J., Park, I.-C.: FIR filter synthesis algorithms for minimizing the delay and the number of adders. IEEE Transactions on Circuits and Systems-II 48, 770–777 (2001)
Dempster, G., Dimirsoy, S.S., Kale, I.: Designing multiplier blocks with low logic design. In: Proceedings IEEE Int. Symp. Circuits and Systems, vol. 5, pp. 773–776 (2002)
Yao, C.-Y., Chen, H.-H., Lin, T.-F., Chien, C.-J., Hsu, C.-T.: A novel commonsubexpression- elmination method for synthesizing fixed-point FIR filters. IEEE Transactions on Circuits and Systems-I 51, 2215–2221 (2004)
von Cölln (Jochens), G., Kruse, L., Schmidt, E., Stammermann, A., Nebel, W.: Power macro-modelling for firm-macros. In: Soudris, D.J., Pirsch, P., Barke, E. (eds.) PATMOS 2000. LNCS, vol. 1918, pp. 24–35. Springer, Heidelberg (2000)
Schmidt, E., Schulz, A., Kruse, L., von Cölln (Jochens), G., Nebel, W.: Automatic Generation of Complexity Functions for High Level Power Analysis. In: Proceedings of PATMOS 2001, pp. 26–35 (2001)
Helms, D., Schmidt, E., Schulz, A.: An Improved Power Macro-Model for Arithmetic Datapath Components. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds.) PATMOS 2002. LNCS, vol. 2451, pp. 16–24. Springer, Heidelberg (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Schulz, A., Schallenberg, A., Helms, D., Schulte, M., Reimer, A., Nebel, W. (2005). A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_16
Download citation
DOI: https://doi.org/10.1007/11556930_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
Online ISBN: 978-3-540-32080-7
eBook Packages: Computer ScienceComputer Science (R0)Springer Nature Proceedings Computer Science
