Abstract
Circuit emulation, using dynamically reconfigurable hardware is a high speed alternative to circuit simulation, especially for large and complex designs. Dynamic reconfiguration enhances the ability to efficiently analyse the test of combinational and sequential circuits by providing statistical information on fault grading, detectability, and signature analysis. In this paper we examine hardware accelleration of static and delay fault simulation, and the accelleration in simulating new BIST techniques.
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© 1994 Springer-Verlag Berlin Heidelberg
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Wieler, R.W., Zhang, Z., McLeod, R.D. (1994). Simulating static and dynamic faults in BIST structures with a FPGA based emulator. In: Hartenstein, R.W., ServÃt, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_94
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DOI: https://doi.org/10.1007/3-540-58419-6_94
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