Abstract
Network traffic monitoring in high-speed links is a challenging task. One of the main bottlenecks of such solution are very often the memory bandwidth and its capacity. This usually forces the designers to apply traffic sampling to handle high rates and extreme traffic mixes. This paper presents a novel approach to a memory management system for network flow monitoring designed for FPGA implementation. Hardware memory management unit offers efficiency that allows its application in multi-gigabit networks, while programmable technology delivers flexibility, that allows to customize solution for specific needs.
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Trzepiński, M., Skowron, K., Korona, M., Rawski, M. (2018). FPGA Implementation of Memory Management for Multigigabit Traffic Monitoring. In: Gruca, A., Czachórski, T., Harezlak, K., Kozielski, S., Piotrowska, A. (eds) Man-Machine Interactions 5. ICMMI 2017. Advances in Intelligent Systems and Computing, vol 659. Springer, Cham. https://doi.org/10.1007/978-3-319-67792-7_54
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DOI: https://doi.org/10.1007/978-3-319-67792-7_54
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