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Statistical estimation of delay fault detectabilities and fault grading

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Abstract

In this paper we present a technique to statistically estimate transition delay and path delay fault coverage. The basic method is an extension of STAFAN to include delay faults. By partitioning a combinational circuit into non-overlapping fanout free logic cones, we accurately calculate the transition sensitization controllabilities of 0 ⇀ 1 and 1 ⇀ 0 transitions of the lines within a fanout free logic cone to the output of the fanout free logic cone for each fanout free logic cone. A strategy to calculate the transition observabilities of fanout stems is proposed. The detectability of a path delay fault is evaluated as the product of the observabilities of the input line to its head gate within each fanout free logic cone on the path multiplied by the transition controllability of the path. When compared with the fault simulations, the estimations of transition delay fault coverage are within 2.3%. Also, the technique gives reasonably good path delay fault coverage estimation for large fault set of the ISCAS85 benchmark circuits.

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  1. Department of Electrical and Computer Engineering, University of Manitoba, R3T 5V6, Winnipeg, Manitoba, Canada

    Zaifu Zhang, Robert D. Mcleod & Gregory E. Bridges

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  1. Zaifu Zhang
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  2. Robert D. Mcleod
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Zhang, Z., Mcleod, R.D. & Bridges, G.E. Statistical estimation of delay fault detectabilities and fault grading. J Electron Test 8, 47–60 (1996). https://doi.org/10.1007/BF00136075

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