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FPGA-based hardware accelerator designed for convolutional residual spiking neural networks

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References

  1. Yun H, Park D. A power-efficient reconfigurable hybrid CNN-SNN accelerator for high performance AI applications. In: Proceedings of IEEE COOL CHIPS, 2025. 1–6

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  2. Zhang Y, Xiang S, Jiang S, et al. Hybrid photonic deep convolutional residual spiking neural networks for text classification. Opt Express, 2023, 31: 28489–28502

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  3. Gao Y, Wang T, Yang Y, et al. Advancing neuromorphic architecture towards emerging spiking neural network on FPGA. IEEE TCAD, 2025, 44: 3465–3478

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Acknowledgements

This work was supported by National Natural Science Foundation of China (Grant Nos. 62204196, 62205258, U24B20137) and Fundamental Research Funds for the Central Universities (Grant No. QTZX23041).

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Authors and Affiliations

  1. State Key Laboratory of Integrated Service Networks, Xidian University, Xi’an, 710071, China

    Yahui Zhang, Shuiying Xiang, Chenyang Du, Tao Zou & Xingxing Guo

  2. State Key Discipline Laboratory of Wide Band gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an, 710071, China

    Yahui Zhang, Shuiying Xiang, Xingxing Guo, Genquan Han & Yue Hao

  3. School of Communications and Information Engineering, Xi’an University of Posts and Telecommunications, Xi’an, 710121, China

    Ling Zheng

  4. CCCC First Highway Way Consultants Co. Ltd., Xi’an, 710075, China

    Licun Yu

Authors
  1. Yahui Zhang
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  2. Shuiying Xiang
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  3. Chenyang Du
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  4. Tao Zou
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  5. Xingxing Guo
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  6. Ling Zheng
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  7. Licun Yu
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  8. Genquan Han
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  9. Yue Hao
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Corresponding author

Correspondence to Shuiying Xiang.

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Zhang, Y., Xiang, S., Du, C. et al. FPGA-based hardware accelerator designed for convolutional residual spiking neural networks. Sci. China Inf. Sci. 69, 139403 (2026). https://doi.org/10.1007/s11432-025-4686-2

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  • DOI: https://doi.org/10.1007/s11432-025-4686-2