close
Skip to main content
Springer Nature Link
Log in

Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT

  • Published:
Save article
View saved research
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

In modern VLSI circuits, power consumption has become a design criteria as well as speed and silicon area or gate count. To guide the designer implementing complex applications with real time constraint on dedicated circuits, we present a High Level Synthesis methodology that provides a Register Transfer Level description of an ASIC, from a behavioral description of an algorithm; this complete methodology uses basic techniques such as selection, assignment or scheduling specified for power optimization, associated with a new approach based on data format optimization. Actually, instead of the usual 32-bit floating-point format, it is power efficient to use a fixed-point format provided overflow and computation noise problems are solved. The application of our method on an usual DSP example (the DWT) shows a power reduction of more than 60%.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+
from $39.99 /Month
  • Starting from 10 chapters or articles per month
  • Access and download chapters and articles from more than 300k books and 2,500 journals
  • Cancel anytime
View plans

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Explore related subjects

Discover the latest articles, books and news in related subjects, suggested using machine learning.

References

  1. A. Bellaouar and M.I. Elmasry, Low-Power Digital VLSI Design: Circuits and Systems, Kluwer Academic Publishers, 1995.

  2. J.M. Rabaey and M. Pedram, Low Power Design Methodologies, Kluwer Academic Publishers, 1996.

  3. E. Macii, M. Pedram, and F. Somenzi, “High-Level Power Modeling, Estimation, and Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 11, 1998, pp. 1061–1079.

    Article  Google Scholar 

  4. P.Vanoostende et al., “Issues in LowPower Design for Telecom” in IEEE, 1995, pp. 591–593.

  5. H.-D. Lin, R.-H. Yan, and D. Yu, “Improving CMOS Speed at Low Supply Voltages,” in IEEE Int. Conf. on Computer Design, 1995, pp. 618–621.

  6. O. Coudert, “Gate sizing: A General Purpose Optimization Approach,”EDAC 96, 1996, pp. 214–218.

  7. P.E. Landman, R. Mehra, and J. Rabaey, “An Integrated CAD Environment for Low Power Design,” IEEE Design and Test of Computers, vol. 13, no. 2, 1996, pp. 72–82.

    Article  Google Scholar 

  8. A. Chandrakasan, S. Sheng, and R.W. Brodersen, “Low Power CMOS Digital Design,” IEEE Journal of Solid State Circuits, vol. 27, no. 4, 1992, pp. 473–484.

    Article  Google Scholar 

  9. E. Martin and J.L. Philippe, Ing´enierie des syst`emes `a microprocesseurs: Applications au traitement du signal et de l'image, Paris, Masson, 1996.

  10. Z. Iqbal, M. Potkonjak, S. Dry, and A. Parker, “Critical Path Minimization Using Retiming and Algebraic Speed-up,” DAC 93, 1993, pp. 573–577.

  11. U. Choudhuy and A. Sangiovanni-Vincentelli, “Automatic Generation of Analytic Models for Interconnect Capacitances,” IEEE Trans. on CAD if IC and Systems, vol. 4, no. 4, 1995, pp. 470–480.

    Article  Google Scholar 

  12. J. Cong and C.K. Koh, “Simultaneous Driver and Wire Sizing for Performance and Power Optimization,” IEEE Trans. on VLSI and Systems, vol. 2, no. 4, 1994, pp. 408–424.

    Article  Google Scholar 

  13. A.H. Farrahi, G.E. T´ellez, and M. Sourafzadeh, “Memory Segmentation to Exploit Sleep Mode Operation,” DAC 95, 1995, pp. 36–41.

  14. A.G. Dickinson and J. Denker, “Adiabatic Dynamic Logic,” IEEE Journal of Solid State Circuits, vol. 30, no. 3, 1995, pp. 311–315.

    Article  Google Scholar 

  15. N. Ohkubo, M. Suzuky, T. Shinto, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, “A 4.4 ns CMOS 54*54-b Multiplier Using Pass-Transistor Multiplexer,” IEEE Journ. of Solid State Circuits, vol. 30, no. 3, 1995, pp. 251–256.

    Article  Google Scholar 

  16. M. Potkonjak, M.B. Srivasta, and A. Chandrakasan, “Multiple Constant Multiplications: Efficient andVersatile Framework and Algorithm for Exploiting Common Sub Expression Elimination,” IEEE Trans on CAD, vol. 15, no. 2, 1995, pp. 151–165.

    Article  Google Scholar 

  17. S. Gailhard, N. Julien, J.-Ph. Diguet, and E. Martin, “How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs,” in 8-th IEEE GLS-VLSI 98, Louisiana, Feb. 1998.

  18. S. Kim and R. Sridhar, “Comparison of Power Consumption Among Asynchronous Design Styles with their Synchronous Counterparts,” IEEE 37th Symp. on Circuits and Systems, vol. 1, pp. 7–10.

  19. P. Day and J.V. Woods, “Investigation into Micropipeline Latch Design Styles,” IEEE Trans. on VLSI, vol. 3, no. 3, 1995, pp. 264–272.

    Article  Google Scholar 

  20. J. Henkel, “Low Power Hardware/Software Partitioning Approach for Core-based Embedded Systems,” in IEEE Proc. of 36th Design Automation Conference DAC 99, New Orleans Louisiana, 1999.

  21. E.Y. Chung, L. Benini, A. Bogliolo, and G.D. Micheli, “Dynamic Power Management for Non-Stationary Service Requests,” Design Automation and Test in Europe, 1999.

  22. H. Kojima, S. Tanaka, and K. Sasaki, “Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry,” IEEE of Journal of Solid State, vol. 30, no. 4, 1995, pp. 432–435.

    Article  Google Scholar 

  23. A. Bellaouar, I.S. Abu-Khater, and M.I. Elmasry, “Low-Power Cmos/Bicmos Drivers and Receivers for On-Chip Interconnects,” IEEE Journal of Solid State Circuits, vol. 30, no. 6, 1995, pp. 696–700.

    Article  Google Scholar 

  24. F.N. Najm, “Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits,” 1995 DAC, 1995, pp. 612–617.

  25. J. Monteiro, S. Devadas, and A. Ghosh, “Retiming Sequential Circuits for Low Power,” IEEE CAD 93, 1993, pp. 398–425.

  26. D. Singh, J.M. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, and T.J. Mozdzen, “Power Conscious CAD Tools and Methodologies: A Perspective,” Proc. of IEEE, vol. 83, no. 4, 1995, pp. 570–594.

    Article  Google Scholar 

  27. M. Alidissa, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, “Precomputation-Based Logic Optimization for Low Power,” IEEE Trans. on VLSI Systems, vol. 2, no. 4, 1994, pp. 426–435.

    Article  Google Scholar 

  28. S. Iman and M. Pedram, “Logic Extraction and Factorization for Low Power,” DAC 95, 1995, pp. 248–252.

  29. A. Raghunathan, N. Jha, and Dey, High-Level Power Analysis and Optimisation, Kluwer Academic Publishers, 1998.

  30. G. Lakshminarayan, A. Raghunathan, K. S. Khouri, N. K. Jha, and S. Dey, “Common-Case Computation: A High-Level Technique for Power and Performance Optimization,” DAC99, 1999, New Orleans, USA.

  31. L. Benini and G. De Micheli, “State Assignment for Low Power Dissipation,” IEEE Journ. of Solid State Circuits, vol. 30, no. 3, 1995, pp. 258–267.

    Article  Google Scholar 

  32. M.R. Stan and W. Burleson, “Bus-Invert Coding for Low Power I/O,” IEEE Trans. on VLSI systems, vol. 3, 1995, pp. 49–58.

    Article  Google Scholar 

  33. J. Frenkil, “Tools and Methodologies for Low-Power Design,” Proceedings of DAC'97, Anaheim, 1997.

  34. Simplex web site, www.simplex.com.

  35. Mentor Graphics web site,www.mentor.com.

  36. Monterey Design web site, www.montereydesign.com.

  37. Synopsys web site, www.synopsys.com.

  38. Avanti web site, www.avanticorp.com.

  39. F. Rouatbi, B. Haroun, and A.J. Al-Khalili, “Power Estimation Tool for Sub-Micron CMOS VLSI Circuits,” IEEE CAD 1992, pp. 204–209.

  40. A. Nabavi-Lishi and N. Rumin, “Delay and Bus Current Evaluation in CMOS Logic Circuits,” IEEE CAD 1992, pp. 198–203.

  41. F. N. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Trans. on VLSI Systems, vol. 4, no. 4, 1994, pp. 446–454.

    Article  Google Scholar 

  42. R. Burch, F. Najm, P. Yang, and T. Trick, “Mc Power: A Monte Carlo Approach to Power Estimation,” IEEE CAD 92, 1992, pp. 90–97.

  43. A. Ghosh, S. Devadas, K. Keutzer, and J. White, “Estimation of Average Switching Activity in Combinatorial and Sequential Circuits,” IEEE DAC 92, 1992, pp. 253–259.

  44. S. Gupta and F.N. Najm, “Power Macromodeling for High Level Power Estimation,” DAC 97, Anaheim USA, 1997.

  45. Xemics web site, www.xemics.ch.

  46. Sent´e web site, www.senteinc.com.

  47. P.E. Landman and J.M. Rabaey, “Architectural Power Analysis: The Dual Bit Method,” IEEE Trans. on VLSI Systems, vol. 3, no. 2, 1995, pp. 173–187.

    Article  Google Scholar 

  48. M.Denoual, D. Saille, D. Chillet, and O. Sentieys, “Mod´elisation et Estimation Haut-Niveau de la Consommation,” 5`eme Workshop AAA, 26–28 janvier 2000 Rocquencourt France, pp. 21–26.

  49. T. Grandpierre, C. Lavarenne, and Y. Sorel, “Optimized Rapid Prototyping for Real-Time Embedded Heterogeneous Multiprocessors,” CODES'99, 7th International Workshop on Hardware/Software Co-Design, Rome, May 1999.

  50. L. Guerra, M. Potkonjak, and J. Rabaey, “A Methodology for Guided Behavioral-Level Optimization,” in IEEE Proc. of 35th Design Automation Conference DAC98, San Francisco, USA, 1998.

  51. L. Guerra, M. Potkonjak, and J. Rabaey, “System-Level Design Guidance Using Algorithm Properties,” IEEE VLSI Signal Processing, vol. VII, 1994, pp. 73–82.

    Google Scholar 

  52. S. Gailhard, N. Julien, and E. Martin, “Adaptative Filters Implementation Performances Under Power Dissipation Constraint,” EUROSIPCO 98, Greece, Sept. 1998.

  53. A.P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R.W. Brodersen, “Optimizing Power Using Transformations,” IEEE Trans. on VLSI Systems, vol. 14, no. 1, 1995, pp. 12–29.

    Google Scholar 

  54. D. Lisky and J. Rabaey, “Early Power Exploration-A World Wide Web Application,” in Proceedings of the 1996 Design Automation Conference, pp. 27–32.

  55. Y. Li and J. Henkel, “A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems,” in IEEE Proceedings of 35th Design Automation Conference DAC98, San Francisco, USA, 1998.

  56. I. Hong, D. Kirovski et al., “Power Optimization of Variable Voltage Core-based Systems,” in IEEE Proc. of 35th Design Automation Conference DAC98, San Francisco, USA, 1998, pp. 176–181.

  57. M. Ercegovac, D. Kirovski, and G. Potkonjak, “Low Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic,” in IEEE Proc. of 36th Design Automation Conference DAC99, New Orleans, USA, pp. 568–573.

  58. E. Martin, O. Sentieys, H. Dubois, and J.-L. Philippe, “GAUT, an Architectural Synthesis Tool for Dedicated Signal Processors,” in Proceedings EURO-DAC 93, 1993.

  59. S. Gailhard, O. Sentieys, N. Julien, and E. Martin, “Are/Time /Power Space Exploration in Module Selection for DSP High Level Synthesis,” in Int. Workshop PATMOS'97, Louvain la Neuve, Belgium, Sept. 97, pp. 35–44.

  60. O. Sentieys, J.-Ph. Diguet, J. L. Philippe, and E. Martin, “Hardware Module Selection for Real Time Pipeline Architectures using Probabilistic Estimation,” in 9th Annual IEEE Inter. ASIC Conf. and Exhibit, 1996, pp. 147–150.

  61. J.M. Tourreilles, C. Nou¨et, and E. Martin, “M´ethode d'implantation d'algorithmes de traitement du signal en pr´ecision finie,”, GRETSI 97 Seizi`eme colloque sur le traitement du signal et des images, Grenoble, du 15 au 19 Sept. 1997.

  62. M. Bellanger, Traitement num´erique du signal, Collection Technique et Scientifique des T´el´ecommunications CNET-ENST, 1984.

  63. M. Antonini, M. Barlaud, P. Mathieu, and I. Daubechies, “Image Coding UsingWavelet Transform,” IEEE Transactions on Image Processing, vol. 1, no. 2, 1992.

  64. A. Grzeszczak, M.K. Mandal, and S. Panchanathan, “VLSI Implementation of Discrete Wavelet Transform,” IEEE Transactions On VLSI Systems, vol. IV, no. 4, 1996.

  65. S. Gailhard, N. Julien, A. Baganne, and E. Martin, “Low Power Design of an Acoustic Echo Canceller Gmdfα Algorithm on Dedicated VLSI,” in 9th IEEE GLS on VLSI, Michigan, USA, March 4–6, 1999, pp. 334–335.

Download references

Author information

Authors and Affiliations

  1. Centre de Recherche rue de Saint Maudé, Lester Université de Bretagne Sud, B.P. 92116, 56321, LORIENT, Cedex

    N. Julien, S. Gailhard & E. Martin

Authors
  1. N. Julien
    View author publications

    Search author on:PubMed Google Scholar

  2. S. Gailhard
    View author publications

    Search author on:PubMed Google Scholar

  3. E. Martin
    View author publications

    Search author on:PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Julien, N., Gailhard, S. & Martin, E. Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 35, 195–211 (2003). https://doi.org/10.1023/A:1023660801499

Download citation

  • Published:

  • Issue date:

  • DOI: https://doi.org/10.1023/A:1023660801499