Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications (Q41625663)
scientific article published on 28 September 2016
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| English | Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications |
scientific article published on 28 September 2016 |
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Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications (English)
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Bilal I Abdulrazzaq
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Omar J Ibrahim
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Shoji Kawahito
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Roslina M Sidek
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Suhaidi Shafie
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Nurul Amziah Md Yunus
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Lini Lee
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Izhal Abdul Halin
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28 September 2016
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28 September 2016
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Identifiers
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28 January 2021
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