{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T21:24:11Z","timestamp":1694640251463},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2010,11,1]],"date-time":"2010-11-01T00:00:00Z","timestamp":1288569600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test. Comput."],"published-print":{"date-parts":[[2010,11]]},"DOI":"10.1109\/mdt.2010.95","type":"journal-article","created":{"date-parts":[[2010,9,7]],"date-time":"2010-09-07T20:20:29Z","timestamp":1283890829000},"page":"36-45","source":"Crossref","is-referenced-by-count":11,"title":["The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane"],"prefix":"10.1109","volume":"27","author":[{"given":"Rajiv","family":"Joshi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rouwaida","family":"Kanj","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anthony","family":"Pelella","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arthur","family":"tuminaro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuen","family":"Chan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687494"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4586009"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDER.2006.307701"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5434074"},{"key":"ref11","first-page":"2564","article-title":"A 5.6 GHz 64 kB Dual-Read Data Cache for the POWER6 Processor","author":"davis","year":"2006","journal-title":"Proc Int l Solid-States Circuits Conf (ISSCC)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2008.4479801"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2008.4656285"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/776063.776066"},{"key":"ref7","article-title":"A Comparative Study of Reliability Estimation Procedures for High Dimensions","author":"schueller","year":"2003","journal-title":"Proc 16th ASCE Eng Mechanics Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2004.1356655"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.229167"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.475.0525"}],"container-title":["IEEE Design & Test of Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/54\/5648484\/05560619.pdf?arnumber=5560619","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:45:50Z","timestamp":1642005950000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5560619\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11]]},"references-count":12,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/mdt.2010.95","relation":{},"ISSN":["0740-7475"],"issn-type":[{"value":"0740-7475","type":"print"}],"subject":[],"published":{"date-parts":[[2010,11]]}}}