{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,27]],"date-time":"2025-05-27T09:05:21Z","timestamp":1748336721604,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1995,11]]},"DOI":"10.1109\/micro.1995.476815","type":"proceedings-article","created":{"date-parts":[[2002,11,19]],"date-time":"2002-11-19T17:10:21Z","timestamp":1037725821000},"page":"82-92","source":"Crossref","is-referenced-by-count":58,"title":["Zero-cycle loads: microarchitecture support for reducing load latency"],"prefix":"10.1109","author":[{"given":"T.M.","family":"Austin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.S.","family":"Sohi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1","volume":"8","author":"gwennap","year":"1994","journal-title":"Microprocessor Report"},{"key":"ref11","first-page":"18","volume":"8","author":"gwennap","year":"1994","journal-title":"Microprocessor Report"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/40.272835"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1989.714563"},{"journal-title":"MIPS RISC Architecture","year":"1992","author":"kane","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/12.48865"},{"journal-title":"An enhanced access and cycle time model for on-chip caches","year":"1994","author":"wilton","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.148323"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"journal-title":"Knapsack A zero-cycle memory hierarchy component","year":"1993","author":"austin","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/800050.801825"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/36177.36193"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/115952.115966"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1147\/rd.374.0547"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"369","DOI":"10.1145\/223982.224447","article-title":"Streamlining data cache access with fast address calculation","author":"austin","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"journal-title":"Compilers Principles Techniques and Tools","year":"1986","author":"aho","key":"ref1"},{"journal-title":"Hardware support for hiding cache latency","year":"1993","author":"golden","key":"ref9"}],"event":{"name":"Proceedings of MICRO'95: 28th Annual IEEE\/ACM International Symposium on Microarchitecture","start":{"date-parts":[[1995,11,29]]},"location":"Ann Arbor, MI, USA","end":{"date-parts":[[1995,12,1]]}},"container-title":["Proceedings of the 28th Annual International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx2\/3464\/10210\/00476815.pdf?arnumber=476815","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,8]],"date-time":"2024-01-08T00:04:31Z","timestamp":1704672271000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/476815\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,11]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/micro.1995.476815","relation":{},"subject":[],"published":{"date-parts":[[1995,11]]}}}