{"id":"https://openalex.org/W4252335726","doi":"https://doi.org/10.1109/micro.1994.717457","title":"The anatomy of the register file in a multiscalar processor","display_name":"The anatomy of the register file in a multiscalar processor","publication_year":2005,"publication_date":"2005-08-24","ids":{"openalex":"https://openalex.org/W4252335726","doi":"https://doi.org/10.1109/micro.1994.717457"},"language":"en","primary_location":{"id":"doi:10.1109/micro.1994.717457","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.1994.717457","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057162184","display_name":"S.E. Breach","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.E. Breach","raw_affiliation_strings":["Computer Sciences Department, University of Wisconsin, Madison, Madison, WI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Sciences Department, University of Wisconsin, Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061687504","display_name":"T.N. Vijaykumar","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T.N. Vijaykumar","raw_affiliation_strings":["Computer Sciences Department, University of Wisconsin, Madison, Madison, WI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Sciences Department, University of Wisconsin, Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108260478","display_name":"Gurindar S. Sohi","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G.S. Sohi","raw_affiliation_strings":["Computer Sciences Department, University of Wisconsin, Madison, Madison, WI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Sciences Department, University of Wisconsin, Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I135310074"],"apc_list":null,"apc_paid":null,"fwci":0.2642,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.6581223,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"181","last_page":"190"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.934912919998169},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.821448028087616},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.7839605212211609},{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.6781402826309204},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.6046850681304932},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5489438772201538},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3704691529273987},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.3347693085670471},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.219511479139328},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12894731760025024}],"concepts":[{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.934912919998169},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.821448028087616},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.7839605212211609},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.6781402826309204},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.6046850681304932},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5489438772201538},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3704691529273987},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.3347693085670471},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.219511479139328},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12894731760025024},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/micro.1994.717457","is_oa":false,"landing_page_url":"https://doi.org/10.1109/micro.1994.717457","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320332222","display_name":"University of Illinois at Urbana-Champaign","ror":"https://ror.org/047426m28"},{"id":"https://openalex.org/F4320337345","display_name":"Office of Naval Research","ror":"https://ror.org/00rk2pe57"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2107916517","https://openalex.org/W2120734674","https://openalex.org/W2128731376","https://openalex.org/W2135270610","https://openalex.org/W2164393230","https://openalex.org/W4230464011","https://openalex.org/W4239600267","https://openalex.org/W4250948896","https://openalex.org/W6680063218"],"related_works":["https://openalex.org/W2224192221","https://openalex.org/W1482836228","https://openalex.org/W2356166161","https://openalex.org/W2014882201","https://openalex.org/W3144620029","https://openalex.org/W2548469345","https://openalex.org/W2130533867","https://openalex.org/W1969937427","https://openalex.org/W2159458033","https://openalex.org/W2483419948"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,6,10,17,43,58,63,69,74,84,87,98,101],"operation":[4,85,99],"of":[5,19,46,65,86,97,100,107],"register":[7,14,23,31,75,88,102],"file":[8,15,76,89,103],"in":[9,37,62],"multiscalar":[11,39],"architecture.":[12],"The":[13],"provides":[16],"appearance":[18],"a":[20,38,53],"logically":[21],"centralized":[22],"file,":[24],"yet":[25],"is":[26,77,90],"implemented":[27],"as":[28],"physically":[29],"decentralized":[30],"files,":[32],"queues,":[33],"and":[34,49,56,79,104],"control":[35],"logic":[36],"processor.":[40],"We":[41],"address":[42],"key":[44],"issues":[45],"storage,":[47],"communication,":[48],"synchronization":[50],"required":[51,71],"for":[52],"successful":[54],"design":[55],"discuss":[57],"complications":[59],"that":[60],"arise":[61],"face":[64],"speculation.":[66],"In":[67],"particular,":[68],"hardware":[70],"to":[72,82],"implement":[73],"detailed,":[78],"software":[80],"support":[81],"streamline":[83],"described.":[91],"Illustrative":[92],"examples":[93],"detailing":[94],"important":[95],"aspects":[96],"an":[105],"evaluation":[106],"its":[108],"effectiveness":[109],"are":[110],"provided.":[111]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}