BHARAT-TPM: Micro-Architecture Design of Scalable Hardware Random Number Generator for a RISC-V Trusted Platform Module.

Aneesh Raveendran Soumya G. Hosmani Raja Sekar K Aneesh Raveendran Vivian Desalphine Haribabu P S. D. Sudarsan BHARAT-TPM: Micro-Architecture Design of Scalable Hardware Random Number Generator for a RISC-V Trusted Platform Module. 109-114 2026 VLSID https://doi.org/10.1109/VLSID68508.2026.00033 conf/vlsid/2026 db/conf/vlsid/vlsid2026.html#HosmaniKRDPS26 Venkata Reddy Kolagatla Aneesh Raveendran Vivian Desalphine Enhancing Performance and Scalability: A Novel Hardware Architecture for 1024-bit Miller-Rabin Primality Testing. 1-6 2024 VDAT https://doi.org/10.1109/VDAT63601.2024.10705670 conf/vdat/2024 db/conf/vdat/vdat2024.html#KolagatlaRD24 Venkata Reddy Kolagatla Aneesh Raveendran Vivian Desalphine A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications. 1-6 2024 VDAT https://doi.org/10.1109/VDAT63601.2024.10705738 conf/vdat/2024 db/conf/vdat/vdat2024.html#KolagatlaRD24a Pranose J. Edavoor Aneesh Raveendran David Selvakumar Vivian Desalphine Shankar G. Dharani Gopal Raut Design and Analysis of Posit Quire Processing Engine for Neural Network Applications. 252-257 2023 VLSID https://doi.org/10.1109/VLSID57277.2023.00059 conf/vlsid/2023 db/conf/vlsid/vlsid2023.html#EdavoorRSDDR23 Annarao Kulkarni Shashikala Gunderao Pattanshetty Aneesh Raveendran David Selvakumar Sandra Jean Vivian Desalphine PositGen-A Verification Suite for Posit Arithmetic. 204-209 2021 VLSID https://doi.org/10.1109/VLSID51830.2021.00040 conf/vlsid/2021 db/conf/vlsid/vlsid2021.html#KulkarniPRSJD21 Sandra Jean Aneesh Raveendran A. David Selvakumar Gagandeep Kaur Shankar G. Dharani Shashikala Gunderao Pattanshetty Vivian Desalphine P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor. 282-287 2021 VLSID https://doi.org/10.1109/VLSID51830.2021.00053 conf/vlsid/2021 db/conf/vlsid/vlsid2021.html#JeanRSKDPD21 Vivian Desalphine Somya Dashora Laxita Mali Suhas K Aneesh Raveendran David Selvakumar Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA. 1-4 2020 VDAT https://doi.org/10.1109/VDAT50263.2020.9190377 conf/vdat/2020 db/conf/vdat/vdat2020.html#DesalphineDMKRS20 Aneesh Raveendran Sandra Jean J. Mervin Vivian Desalphine David Selvakumar A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture. 207-212 2020 VLSID https://doi.org/10.1109/VLSID49098.2020.00053 conf/vlsid/2020 db/conf/vlsid/vlsid2020.html#RaveendranJJDS20 Aneesh Raveendran Sandra Jean J. Mervin Vivian Desalphine A. David Selvakumar RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor. 482-495 2019 VDAT https://doi.org/10.1007/978-981-32-9767-8_40 conf/vdat/2019 db/conf/vdat/vdat2019.html#RaveendranJMVS19 Aneesh Raveendran Vinay Kumar Vivian Desalphine David Selvakumar Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU. 496-509 2019 VDAT https://doi.org/10.1007/978-981-32-9767-8_41 conf/vdat/2019 db/conf/vdat/vdat2019.html#RaveendranKVS19 Vinayak Patil Aneesh Raveendran P. M. Sobha A. David Selvakumar Vivian Desalphine Out of order floating point coprocessor for RISC V ISA. 1-7 2015 VDAT https://doi.org/10.1109/ISVDAT.2015.7208116 https://doi.ieeecomputersociety.org/10.1109/ISVDAT.2015.7208116 conf/vdat/2015 db/conf/vdat/vdat2015.html#PatilRSSV15 Aneesh Raveendran Vinayak Patil Vivian Desalphine P. M. Sobha A. David Selvakumar RISC-V out-of-order data conversion co-processor. 1-2 2015 VDAT https://doi.org/10.1109/ISVDAT.2015.7208117 https://doi.ieeecomputersociety.org/10.1109/ISVDAT.2015.7208117 conf/vdat/2015 db/conf/vdat/vdat2015.html#RaveendranPDSS15 Somya Dashora Vivian Desalphine Shankar G. Dharani Pranose J. Edavoor Soumya G. Hosmani Sandra Jean Raja Sekar K Suhas K Gagandeep Kaur Venkata Reddy Kolagatla Annarao Kulkarni Vinay Kumar Laxita Mali J. Mervin Haribabu P Vinayak Patil Shashikala Gunderao Pattanshetty Gopal Raut A. David SelvakumarDavid Selvakumar P. M. Sobha S. D. Sudarsan