<?xml version="1.0"?>
<dblpperson name="Cesar Boatella Polo" pid="230/6825" n="1">
<person key="homepages/230/6825" mdate="2018-11-28">
<author pid="230/6825">Cesar Boatella Polo</author>
</person>
<r><inproceedings key="conf/ahs/SterponeABDLGAP18" mdate="2021-10-14">
<author orcid="0000-0002-3080-2560" pid="66/3508">Luca Sterpone</author>
<author orcid="0000-0002-9169-6140" pid="169/9251">Sarah Azimi</author>
<author pid="206/3084">Ludovica Bozzoli</author>
<author pid="80/609">Boyang Du</author>
<author orcid="0000-0002-5002-3679" pid="78/2340">Thomas Lange</author>
<author pid="159/3419">Maximilien Glorieux</author>
<author pid="36/4660">Dan Alexandrescu</author>
<author pid="230/6825">Cesar Boatella Polo</author>
<author pid="00/10034">David Merodio Codinachs</author>
<title>A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs.</title>
<pages>120-126</pages>
<year>2018</year>
<booktitle>AHS</booktitle>
<ee>https://doi.org/10.1109/AHS.2018.8541474</ee>
<crossref>conf/ahs/2018</crossref>
<url>db/conf/ahs/ahs2018.html#SterponeABDLGAP18</url>
</inproceedings>
</r>
<coauthors n="8" nc="1">
<co c="0"><na f="a/Alexandrescu:Dan" pid="36/4660">Dan Alexandrescu</na></co>
<co c="0"><na f="a/Azimi:Sarah" pid="169/9251">Sarah Azimi</na></co>
<co c="0"><na f="b/Bozzoli:Ludovica" pid="206/3084">Ludovica Bozzoli</na></co>
<co c="0"><na f="c/Codinachs:David_Merodio" pid="00/10034">David Merodio Codinachs</na></co>
<co c="0"><na f="d/Du:Boyang" pid="80/609">Boyang Du</na></co>
<co c="0"><na f="g/Glorieux:Maximilien" pid="159/3419">Maximilien Glorieux</na></co>
<co c="0"><na f="l/Lange:Thomas" pid="78/2340">Thomas Lange</na></co>
<co c="0"><na f="s/Sterpone:Luca" pid="66/3508">Luca Sterpone</na></co>
</coauthors>
</dblpperson>

