<?xml version="1.0"?>
<dblpperson name="Mark S. Milshtein" pid="317/4605" n="1">
<person key="homepages/317/4605" mdate="2022-04-04">
<author pid="317/4605">Mark S. Milshtein</author>
</person>
<r><article key="journals/jssc/HintonUSBCRCFMS01" mdate="2022-04-06">
<author pid="15/10281">Glenn Hinton</author>
<author pid="30/4772">Michael Upton</author>
<author pid="317/4746">David J. Sager</author>
<author pid="92/1427">Darrell Boggs</author>
<author pid="128/9388">Douglas M. Carmean</author>
<author pid="31/6655">Patrice Roussel</author>
<author pid="38/3130">Terry I. Chappell</author>
<author pid="92/8835">Thomas D. Fletcher</author>
<author pid="317/4605">Mark S. Milshtein</author>
<author pid="317/4555">Milo Sprague</author>
<author pid="317/5077">Samie Samaan</author>
<author pid="255/6628">Robert Murray</author>
<title>A 0.18-&#956;m CMOS IA-32 processor with a 4-GHz integer execution unit.</title>
<pages>1617-1627</pages>
<year>2001</year>
<volume>36</volume>
<journal>IEEE J. Solid State Circuits</journal>
<number>11</number>
<ee>https://doi.org/10.1109/4.962281</ee>
<url>db/journals/jssc/jssc36.html#HintonUSBCRCFMS01</url>
</article>
</r>
<coauthors n="11" nc="1">
<co c="0"><na f="b/Boggs:Darrell" pid="92/1427">Darrell Boggs</na></co>
<co c="0"><na f="c/Carmean:Douglas_M=" pid="128/9388">Douglas M. Carmean</na></co>
<co c="0"><na f="c/Chappell:Terry_I=" pid="38/3130">Terry I. Chappell</na></co>
<co c="0"><na f="f/Fletcher:Thomas_D=" pid="92/8835">Thomas D. Fletcher</na></co>
<co c="0"><na f="h/Hinton:Glenn" pid="15/10281">Glenn Hinton</na></co>
<co c="0"><na f="m/Murray:Robert" pid="255/6628">Robert Murray</na></co>
<co c="0"><na f="r/Roussel:Patrice" pid="31/6655">Patrice Roussel</na></co>
<co c="0"><na f="s/Sager:David_J=" pid="317/4746">David J. Sager</na></co>
<co c="0"><na f="s/Samaan:Samie" pid="317/5077">Samie Samaan</na></co>
<co c="0"><na f="s/Sprague:Milo" pid="317/4555">Milo Sprague</na></co>
<co c="0"><na f="u/Upton:Michael" pid="30/4772">Michael Upton</na></co>
</coauthors>
</dblpperson>

