A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking.

Prasenjit Biswas Prasenjit Biswas Sarit Pal Sunil P. Khatri A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking. 114-123 2020 ICICT https://doi.org/10.1109/ICICT50521.2020.00026 conf/icict2/2020 db/conf/icict2/icict2020.html#BiswasPK20 Prasenjit Biswas D. M. H. Walker Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. 141-146 2017 VLSID https://doi.org/10.1109/VLSID.2017.63 https://doi.ieeecomputersociety.org/10.1109/VLSID.2017.63 conf/vlsid/2017 db/conf/vlsid/vlsid2017.html#BiswasW17 Kamal Sarkar Debanjan Das Indra Banerjee Mamta Kumari Prasenjit Biswas JU_KS_Group@FIRE 2016: Consumer Health Information Search. 208-213 2016 FIRE (Working Notes) https://ceur-ws.org/Vol-1737/T5-5.pdf conf/fire/2016w db/conf/fire/fire2016w.html#SarkarDBKB16

Kamal Sarkar Debanjan Das Indra Banerjee Mamta Kumari Prasenjit Biswas JU_KS_Group@FIRE 2016: Consumer Health Information Search. 2016 abs/1612.08178 CoRR http://arxiv.org/abs/1612.08178 db/journals/corr/corr1612.html#SarkarDBKB16

Prasenjit Biswas Pramod P. Udupa Rajdeep Mondal Keshavan Varadarajan Mythri Alle S. K. Nandy 0001 Ranjani Narayan Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. 161-166 2010 ISVLSI https://doi.org/10.1109/ISVLSI.2010.65 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2010.65 conf/isvlsi/2010 db/conf/isvlsi/isvlsi2010.html#BiswasUMVANN10 Prasenjit Biswas Keshavan Varadarajan Mythri Alle S. K. Nandy 0001 Ranjani Narayan Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. 265-272 2010 ICSAMOS https://doi.org/10.1109/ICSAMOS.2010.5642058 conf/samos/2010ic db/conf/samos/samos2010ic.html#BiswasVANN10

Mythri Alle Keshavan Varadarajan Alexander Fell C. Ramesh Reddy Joseph Nimmy Saptarsi Das Prasenjit Biswas Jugantor Chetia Adarsha Rao S. K. Nandy 0001 Ranjani Narayan REDEFINE: Runtime reconfigurable polymorphic ASIC. 2009 9 ACM Trans. Embed. Comput. Syst. 2 https://doi.org/10.1145/1596543.1596545 db/journals/tecs/tecs9.html#AlleVFRNDBCRNN09 11:1-11:48

Alexander Fell Mythri Alle Keshavan Varadarajan Prasenjit Biswas Saptarsi Das Jugantor Chetia S. K. Nandy 0001 Ranjani Narayan Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. 127-136 2009 CASES https://doi.org/10.1145/1629395.1629414 conf/cases/2009 db/conf/cases/cases2009.html#FellAVBDCNN09 Alexander Fell Prasenjit Biswas Jugantor Chetia S. K. Nandy 0001 Ranjani Narayan Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. 251-254 2009 SoCC https://doi.org/10.1109/SOCCON.2009.5398048 conf/socc/2009 db/conf/socc/socc2009.html#FellBCNN09

Prasenjit Biswas Atsushi Hasegawa Srinivas Mandaville Mark Debbage Andy Sturges Fumio Arakawa Yasuhiko Saito Kunio Uchiyama SH-5: The 64-Bit SuperH Architecture. 28-39 2000 20 IEEE Micro 4 https://doi.org/10.1109/40.865864 http://doi.ieeecomputersociety.org/10.1109/40.865864 db/journals/micro/micro20.html#BiswasHMDSASU00

Prasenjit Biswas Andy Freeman Kouji Yamada Norio Nakagawa Kunio Uchiyama Functional verification of the superscalar SH-4 microprocessor. 115-120 1997 COMPCON https://doi.org/10.1109/CMPCON.1997.584682 https://doi.ieeecomputersociety.org/10.1109/CMPCON.1997.584682 conf/compcon/1997 db/conf/compcon/compcon1997.html#BiswasFYNU97

Atsushi Hasegawa Ikuya Kawasaki Kouji Yamada Shinichi Yoshioka Shumpei Kawasaki Prasenjit Biswas SH3: high code density, low power. 11-19 1995 15 IEEE Micro 6 https://doi.org/10.1109/40.476254 http://doi.ieeecomputersociety.org/10.1109/40.476254 db/journals/micro/micro15.html#HasegawaKYYKB95

Surapong Auwatanamongkol Andrzej Ciepielewski Prasenjit Biswas Cut and Side-Effects in a Data-Driven Implementation of Prolog. 223-250 1994 12 New Gener. Comput. 3 db/journals/ngc/ngc12.html#AuwatanamongkolCB94 https://doi.org/10.1007/BF03037344

Dagung Lu Prasenjit Biswas An extended scheduling technique for software pipelining. 99-103 1993 37 Microprocess. Microprogramming 1-5 https://doi.org/10.1016/0165-6074(93)90025-G db/journals/jsa/jsa37.html#LuB93

Behrooz A. Shirazi Krishna M. Kavi Ali R. Hurson Prasenjit Biswas PARSA: A Parallel Program Scheduling and Assessment Environment. 68-72 1993 conf/icpp/1993-2 ICPP (2) db/conf/icpp/icpp1993-2.html#ShiraziKHB93 https://doi.org/10.1109/ICPP.1993.138 https://doi.ieeecomputersociety.org/10.1109/ICPP.1993.138

Syhy-Chang Su Prasenjit Biswas A memory-mapped interprocessor communication architecture using FIFO RAMs. 187-191 1992 34 Microprocess. Microprogramming 1-5 https://doi.org/10.1016/0165-6074(92)90131-P db/journals/jsa/jsa34.html#SuB92

Gautam Dewan Prasenjit Biswas A snooping cache coherency protocol for hierarchically organized multiprocessors. 105-111 1991 31 Microprocessing and Microprogramming 1-5 https://doi.org/10.1016/S0165-6074(08)80053-1 db/journals/jsa/jsa31.html#DewanB91

Surapong Auwatanamongkol Prasenjit Biswas A Hybrid Architecture and Adaptive Scheduling for Parallel Execution of Logic Programs. 17-20 1991 conf/icpp/1991-1 ICPP (1) db/conf/icpp/icpp1991-1.html#AuwatanamongkolB91

Shyh-Chang Su Prasenjit Biswas Scheduling demand-driven parallel logic programs on transputers. 37-41 1990 28 Microprocessing and Microprogramming 1-5 https://doi.org/10.1016/0165-6074(90)90145-Y db/journals/jsa/jsa28.html#SuB90

Prasenjit Biswas Jin Chen A demand-driven macro-dataflow schema for distributed graph reduction on multiple G-machines. 161-166 1990 28 Microprocessing and Microprogramming 1-5 https://doi.org/10.1016/0165-6074(90)90167-8 db/journals/jsa/jsa28.html#BiswasC90

Chin-Feng Fan Prasenjit Biswas Abstract machine LORAP II and experiments in process grain size determination for parallel execution of logic programs. 685-692 1989 TAI https://doi.org/10.1109/TAI.1989.65382 https://doi.ieeecomputersociety.org/10.1109/TAI.1989.65382 conf/ictai/1989 db/conf/ictai/ictai1989.html#FanB89 Prasenjit Biswas Chien-Chao Tseng LogDf: A Data-Driven Abstract Machine Model for Parallel Execution of Logic Programs. 1059-1070 1988 conf/fgcs/1988 FGCS db/conf/fgcs/fgcs88.html#BiswasT88 Prasenjit Biswas Shyh-Chang Su David Y. Y. Yun A Scalable Abstract Machine Model to Support Limited-OR (LOR) / Restricted-AND Parallelism (RAP) in Logic Programs. 1160-1179 1988 conf/iclp/1988 ICLP/SLP db/conf/iclp/iclp88.html#BiswasSY88 Chien-Chao Tseng Prasenjit Biswas A Data-Driven Parallel Execution Model for Logic Programs. 1204-1222 1988 conf/iclp/1988 ICLP/SLP db/conf/iclp/iclp88.html#TsengB88 Prasenjit Biswas Arun K. Majumdar A Fuzzy Hybrid Model for Pattern Classification. 183-192 1988 conf/par/1988 Pattern Recognition db/conf/par/par1988.html#BiswasM88 https://doi.org/10.1007/3-540-19036-8_17

Prasenjit Biswas Subrata Dasgupta Architectural support for variable addressing in Ada - A design approach. 51-72 1985 14 Int. J. Parallel Program. 1 https://doi.org/10.1007/BF00990901 db/journals/ijpp/ijpp14.html#BiswasD85

Prasenjit Biswas Arun K. Majumdar A supervised learning algorithm for hierarchical classification of fuzzy patterns. 91-106 1983 31 Inf. Sci. 2 https://doi.org/10.1016/0020-0255(83)90028-2 db/journals/isci/isci31.html#BiswasM83

Mythri Alle Fumio Arakawa Surapong Auwatanamongkol Indra Banerjee Jin Chen Jugantor Chetia Andrzej Ciepielewski Debanjan Das Saptarsi Das Subrata Dasgupta Mark Debbage Gautam Dewan Chin-Feng Fan Alexander Fell Andy Freeman Atsushi Hasegawa Ali R. Hurson Krishna M. Kavi Ikuya Kawasaki Shumpei Kawasaki Sunil P. Khatri Mamta Kumari Dagung Lu Arun K. Majumdar Srinivas Mandaville Rajdeep Mondal Norio Nakagawa S. K. Nandy 0001 Ranjani Narayan Joseph Nimmy Sarit Pal Adarsha Rao C. Ramesh Reddy Yasuhiko Saito Kamal Sarkar Behrooz A. Shirazi Andy Sturges Shyh-Chang Su Syhy-Chang Su Chien-Chao Tseng Kunio Uchiyama Pramod P. Udupa Keshavan Varadarajan D. M. H. Walker Kouji Yamada Shinichi Yoshioka David Y. Y. Yun