Psychological features of dispute content and public acceptance of AI in legal adjudication: evidence for systematic variation beyond individual differences.

Masahiro Fujita Masahiro Fujita 0001 https://orcid.org/0000-0001-7078-6844 https://www.wikidata.org/entity/Q92681679 Weill Cornell Medical College, New York, NY, USA Masahiro Fujita 0002 https://orcid.org/0009-0006-4646-6975 Sony, Tokyo, Japan Masahiro Fujita 0003 https://orcid.org/0009-0003-3054-8579 ArkEdge Space Inc., Tokyo, Japan Masahiro Fujita 0004 University of Tokyo, VLSI Design and Education Center (VDEC), Japan Fujitsu Laboratories of America, Sunnyvale, CA, USA University of Tokyo, Department of information engineering, Japan https://orcid.org/0000-0002-6516-4175

Masahiro Fujita Eiichiro Watamura Psychological features of dispute content and public acceptance of AI in legal adjudication: evidence for systematic variation beyond individual differences. 2026 9 Frontiers Artif. Intell. https://doi.org/10.3389/frai.2026.1716094 db/journals/frai/frai9.html#FujitaW26 streams/journals/frai

Wataru Hatakeyama Shinnosuke Nozaki Ayumi Serizawa Mizuho Yoshihira Masahiro Fujita Ayako Yoshimura Tetsushi Ohki Masakatsu Nishigaki Multi-Observed Authentication: A secure and usable authentication based on multi-point observation of a single physical credential. 1-6 2024 APSIPA https://doi.org/10.1109/APSIPAASC63619.2025.10848968 conf/apsipa/2024 db/conf/apsipa/apsipa2024.html#HatakeyamaNSYFY24 Yusuke Kimura Shaowen Li Hiroyuki Sato 0002 Masahiro Fujita Decision Diagram vs. State Vector: A Comparative Study on Quantum Computing Simulation Efficiency. 757-763 2024 QCE https://doi.org/10.1109/QCE60285.2024.00095 conf/qce/2024 db/conf/qce/qce2024.html#KimuraLSF24 streams/conf/qce Yusuke Kimura Shaowen Li Hiroyuki Sato 0002 Masahiro Fujita Accelerating Decision Diagram-based Multi-node Quantum Simulation with Ring Communication and Automatic SWAP Insertion. 107-115 2024 QSW https://doi.org/10.1109/QSW62656.2024.00025 conf/qsw/2024 db/conf/qsw/qsw2024.html#KimuraLSF24 streams/conf/qsw

Yusuke Kimura Shaowen Li Hiroyuki Sato Masahiro Fujita Accelerating Decision Diagram-based Multi-node Quantum Simulation with Ring Communication and Automatic SWAP Insertion. 2024 abs/2405.09033 CoRR https://doi.org/10.48550/arXiv.2405.09033 db/journals/corr/corr2405.html#abs-2405-09033

Shaowen Li Yusuke Kimura Hiroyuki Sato 0002 Junwei Yu Masahiro Fujita Parallelizing quantum simulation with decision diagrams. 149-154 2023 QSW https://doi.org/10.1109/QSW59989.2023.00026 conf/qsw/2023 db/conf/qsw/qsw2023.html#LiKSYF23

Shaowen Li Yusuke Kimura Hiroyuki Sato Junwei Yu Masahiro Fujita Parallelizing quantum simulation with decision diagrams. 2023 abs/2312.01570 CoRR https://doi.org/10.48550/arXiv.2312.01570 db/journals/corr/corr2312.html#abs-2312-01570

Masahiro Fujita Yasuoki Iida Mitsuhiro Hattori Tadakazu Yamanaka Nori Matsuda Satoshi Ito Hiroaki Kikuchi Proposal of anonymization dictionary using disclosed statements by business operators. 100490 2022 18 Internet Things https://doi.org/10.1016/j.iot.2021.100490 db/journals/iot/iot18.html#FujitaIHYMIK22

Mingfei Yu Yukio Miyasaka Masahiro Fujita Parallel Scheduling Attention Mechanism: Generalization and Optimization. 2-15 2022 15 IPSJ Trans. Syst. LSI Des. Methodol. https://doi.org/10.2197/ipsjtsldm.15.2 db/journals/ipsj/ipsj15.html#YuMF22

Xinpei Zhang Yi Ding Mingfei Yu Shin-ichi O'Uchi Masahiro Fujita Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models. 1-6 2022 ISQED https://doi.org/10.1109/ISQED54688.2022.9806238 conf/isqed/2022 db/conf/isqed/isqed2022.html#ZhangDYOF22 Jitendra Kumar Asutosh Srivastava Masahiro Fujita Formal Analysis of Integer Multipliers by building Binary Decision Diagram of Adder Trees. 58-63 2022 ISQED https://doi.org/10.1109/ISQED54688.2022.9806278 conf/isqed/2022 db/conf/isqed/isqed2022.html#KumarSF22 Shinnosuke Nozaki Ayumi Serizawa Mizuho Yoshihira Masahiro Fujita Yoichi Shibata Tadakazu Yamanaka Nori Matsuda Tetsushi Ohki Masakatsu Nishigaki Multi-observed Multi-factor Authentication: A Multi-factor Authentication Using Single Credential. 201-211 2022 NBiS https://doi.org/10.1007/978-3-031-14314-4_20 conf/nbis/2022 db/conf/nbis/nbis2022.html#NozakiSYFSYMON22 Heming Sun Qingyang Yi Fangzheng Lin Lu Yu 0003 Jiro Katto Masahiro Fujita Real-time Learned Image Codec on FPGA. 1 2022 VCIP https://doi.org/10.1109/VCIP56404.2022.10008876 conf/vcip/2022 db/conf/vcip/vcip2022.html#SunYLYKF22 Mingfei Yu Ruitao Gao Masahiro Fujita A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure. 518-523 2021 ASP-DAC https://doi.org/10.1145/3394885.3431422 conf/aspdac/2021 db/conf/aspdac/aspdac2021.html#YuGF21 Yukio Miyasaka Xinpei Zhang Mingfei Yu Qingyang Yi Masahiro Fujita Logic Synthesis for Generalization and Learning Addition. 1032-1037 2021 DATE https://doi.org/10.23919/DATE51398.2021.9474169 conf/date/2021 db/conf/date/date2021.html#MiyasakaZYYF21 Masahiro Fujita Yasuoki Iida Mitsuhiro Hattori Tadakazu Yamanaka Nori Matsuda Satoshi Ito Hiroaki Kikuchi Proposal and Development of Anonymization Dictionary Using Public Information Disclosed by Anonymously Processed Information Handling Business Operators. 30-39 2021 IMIS https://doi.org/10.1007/978-3-030-79728-7_4 conf/imis/2021 db/conf/imis/imis2021.html#FujitaIHYMIK21 Hiroaki Kikuchi Atsuki Ono Satoshi Ito Masahiro Fujita Tadakazu Yamanaka Web Crawler for an Anonymously Processed Information Database. 501-510 2021 IMIS https://doi.org/10.1007/978-3-030-79728-7_51 conf/imis/2021 db/conf/imis/imis2021.html#KikuchiOIFY21 Ryogo Koikel Masahiro Fujita Efficient Reachability Analysis Based on Inductive Invariant Using X-value Based Flipflop Selection. 34-40 2021 ISQED https://doi.org/10.1109/ISQED51717.2021.9424357 conf/isqed/2021 db/conf/isqed/isqed2021.html#KoikelF21

Qingyang Yi Heming Sun Masahiro Fujita FPGA Based Accelerator for Neural Networks Computation with Flexible Pipelining. 2021 abs/2112.15443 CoRR https://arxiv.org/abs/2112.15443 db/journals/corr/corr2112.html#abs-2112-15443

Motoyasu Tanaka Kazuyuki Kon Mizuki Nakajima Nobutaka Matsumoto Shinnosuke Fukumura Kosuke Fukui Hidemasa Sawabe Masahiro Fujita Kenjiro Tadakuma Development and field test of the articulated mobile robot T2 Snake-4 for plant disaster prevention. 70-88 2020 34 Adv. Robotics 2 https://doi.org/10.1080/01691864.2019.1680316 db/journals/ar/ar34.html#TanakaKNMFFSFT20

Nobutaka Matsumoto Motoyasu Tanaka Mizuki Nakajima Masahiro Fujita Kenjiro Tadakuma Development of a folding arm on an articulated mobile robot for plant disaster prevention. 89-103 2020 34 Adv. Robotics 2 https://doi.org/10.1080/01691864.2019.1689167 https://www.wikidata.org/entity/Q126802485 db/journals/ar/ar34.html#MatsumotoTNFT20

Masahiro Fujita Yukiyasu Domae Akio Noda Gustavo Alfonso Garcia Ricardez Tatsuya Nagatani Andy Zeng 0001 Shuran Song Alberto Rodriguez 0003 Albert J. Causo I-Ming Chen 0001 Tsukasa Ogasawara What are the important technologies for bin picking? Technology analysis of robots in competitions based on a set of performance metrics. 560-574 2020 34 Adv. Robotics 7-8 https://doi.org/10.1080/01691864.2019.1698463 https://www.wikidata.org/entity/Q126575515 db/journals/ar/ar34.html#FujitaDNRNZSRCC20

Kenji Ono Jorji Nonaka Tomohiro Kawanabe Masahiro Fujita Kentaro Oku Kazuma Hatta HIVE: A cross-platform, modular visualization framework for large-scale data sets. 875-883 2020 112 Future Gener. Comput. Syst. https://doi.org/10.1016/j.future.2020.06.056 db/journals/fgcs/fgcs112.html#OnoNKFOH20

Yukio Miyasaka Akihiro Goda Ashish Mittal Masahiro Fujita Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication. 31-34 2020 13 IPSJ Trans. Syst. LSI Des. Methodol. https://doi.org/10.2197/ipsjtsldm.13.31 db/journals/ipsj/ipsj13.html#MiyasakaGMF20

Yuya Shiomi Genki Sugimoto Ayaka Sugimoto Kota Uehara Masahiro Fujita Yuto Mano Tetsushi Ohki Masakatsu Nishigaki Micro Biometric Authentication Using Fingernail Surfaces: A Study of Practical Use. 1330-1340 2020 AINA https://doi.org/10.1007/978-3-030-44041-1_113 conf/aina/2020 db/conf/aina/aina2020.html#ShiomiSSUFMON20 Zolboo Byambadorj Koji Asami Takahiro J. Yamaguchi Akio Higo Masahiro Fujita Tetsuya Iizuka Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing. 1-6 2020 ATS https://doi.org/10.1109/ATS49688.2020.9301596 conf/ats/2020 db/conf/ats/ats2020.html#ByambadorjAYHFI20 Yukio Miyasaka Masahiro Fujita SAT-Based Data-Flow Mapping Onto Array Processor. 22-27 2020 VLSI-SOC https://doi.org/10.1109/VLSI-SOC46417.2020.9344093 conf/vlsi/2020 db/conf/vlsi/vlsisoc2020.html#MiyasakaF20 Yukio Miyasaka Masahiro Fujita Alan Mishchenko John Wawrzynek SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. 113-131 2020 VLSI-SoC (Selected Papers) https://doi.org/10.1007/978-3-030-81641-4_6 conf/vlsi/2020socs db/conf/vlsi/vlsisoc2020s.html#MiyasakaFMW20

Mingfei Yu Masahiro Fujita Parallel Scheduling Self-attention Mechanism: Generalization and Optimization. 2020 abs/2012.01114 CoRR https://arxiv.org/abs/2012.01114 db/journals/corr/corr2012.html#abs-2012-01114

Masoud Shiroei Bijan Alizadeh Masahiro Fujita Data-path aware high-level ECO synthesis. 88-96 2019 65 Integr. https://doi.org/10.1016/j.vlsi.2018.11.006 https://www.wikidata.org/entity/Q128853336 db/journals/integration/integration65.html#ShiroeiAF19

Motoyasu Tanaka Kenjiro Tadakuma Mizuki Nakajima Masahiro Fujita Task-Space Control of Articulated Mobile Robots With a Soft Gripper for Operations. 135-146 2019 35 IEEE Trans. Robotics 1 https://doi.org/10.1109/TRO.2018.2878361 db/journals/trob/trob35.html#TanakaTNF19

Kota Uehara Kohei Mukaiyama Masahiro Fujita Hiroki Nishikawa Takumi Yamamoto Kiyoto Kawauchi Masakatsu Nishigaki Basic Study on Targeted E-mail Attack Method Using OSINT. 1329-1341 2019 AINA https://doi.org/10.1007/978-3-030-15032-7_111 conf/aina/2019 db/conf/aina/aina2019.html#UeharaMFNYKN19 Masahiro Fujita Yukiyasu Domae Ryosuke Kawanishi Gustavo Alfonso Garcia Ricardez Kenta Kato Koji Shiratsuchi Rintaro Haraguchi Ryosuke Araki Hironobu Fujiyoshi Shuichi Akizuki Manabu Hashimoto Albert J. Causo Akio Noda Haruhisa Okuda Tsukasa Ogasawara Bin-picking Robot using a Multi-gripper Switching Strategy based on Object Sparseness. 1540-1547 2019 CASE https://doi.org/10.1109/COASE.2019.8842977 conf/case/2019 db/conf/case/case2019.html#FujitaDKRKSHAFA19 Masahiro Fujita Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions. 109-116 2019 ISPD https://doi.org/10.1145/3299902.3311069 https://www.wikidata.org/entity/Q130844073 conf/ispd/2019 db/conf/ispd/ispd2019.html#Fujita19 Yukio Miyasaka Ashish Mittal Masahiro Fujita Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing. 45-51 2019 ISQED https://doi.org/10.1109/ISQED.2019.8697224 conf/isqed/2019 db/conf/isqed/isqed2019.html#MiyasakaMF19 Masahiro Fujita AI x Robotics: Technology Challenges and Opportunities in Sensors, Actuators, and Integrated Circuits. 276-278 2019 ISSCC https://doi.org/10.1109/ISSCC.2019.8662358 conf/isscc/2019 db/conf/isscc/isscc2019.html#Fujita19 Takahiko Ishizu Yuto Yakubo Kazuma Furutani Atsuo Isobe Masashi Fujita Tomoaki Atsumi Yoshinori Ando Tsutomu Murakawa Kiyoshi Kato Masahiro Fujita Shunpei Yamazaki A 48 MHz 880-nW Standby Power Normally-Off MCU with 1 Clock Full Backup and 4.69-μs Wakeup Featuring 60-nm Crystalline In-Ga-Zn Oxide BEOL-FETs. 48- 2019 VLSI Circuits https://doi.org/10.23919/VLSIC.2019.8778076 conf/vlsic/2019 db/conf/vlsic/vlsic2019.html#IshizuYFIFAAMKF19 Fumitoshi Matsuno Tetsushi Kamegawa Wei Qi Tatsuya Takemori Motoyasu Tanaka Mizuki Nakajima Kenjiro Tadakuma Masahiro Fujita Yosuke Suzuki Katsutoshi Itoyama Hiroshi G. Okuno Yoshiaki Bando Tomofumi Fujiwara Satoshi Tadokoro Development of Tough Snake Robot Systems. 267-326 2019 Disaster Robotics https://doi.org/10.1007/978-3-030-05321-5_6 series/star/128 db/series/star/star128.html#MatsunoKQTTNTFSIOBFT19

Masahiro Fujita Suguru Ikeda Toshiaki Fujimoto Toshihiko Shimizu Shuhei Ikemoto Takeshi Miyamoto Development of universal vacuum gripper for wall-climbing robot. 283-296 2018 32 Adv. Robotics 6 https://doi.org/10.1080/01691864.2018.1447238 https://www.wikidata.org/entity/Q58025535 db/journals/ar/ar32.html#FujitaIFSIM18

Masahiro Fujita Kenjiro Tadakuma Hirone Komatsu Eri Takane Akito Nomura Tomoya Ichimura Masashi Konyo Satoshi Tadokoro Jamming layered membrane gripper mechanism for grasping differently shaped-objects without excessive pushing force for search and rescue missions. 590-604 2018 32 Adv. Robotics 11 https://doi.org/10.1080/01691864.2018.1451368 https://www.wikidata.org/entity/Q58026876 db/journals/ar/ar32.html#FujitaTKTNIKT18

Jorji Nonaka Kenji Ono Masahiro Fujita 234Compositor: A flexible parallel image compositing framework for massively parallel visualization environments. 647-655 2018 82 Future Gener. Comput. Syst. https://doi.org/10.1016/j.future.2017.02.011 db/journals/fgcs/fgcs82.html#NonakaOF18

Kenjiro Tadakuma Eri Takane Masahiro Fujita Akito Nomura Hirone Komatsu Masashi Konyo Satoshi Tadokoro Planar Omnidirectional Crawler Mobile Mechanism - Development of Actual Mechanical Prototype and Basic Experiments. 395-402 2018 3 IEEE Robotics Autom. Lett. 1 https://doi.org/10.1109/LRA.2017.2739101 db/journals/ral/ral3.html#TadakumaTFNKKT18

Hiroyuki Suzuki Hiromasa Masuda Kazuo Hongo Ryuta Horie Shunsuke Yajima Yuki Itotani Masahiro Fujita Ken'ichiro Nagasaka Development and Testing of Force-Sensing Forceps Using FBG for Bilateral Micro-Operation System. 4281-4288 2018 3 IEEE Robotics Autom. Lett. 4 https://doi.org/10.1109/LRA.2018.2864771 db/journals/ral/ral3.html#SuzukiMHHYIFN18

Jorji Nonaka Motohiko Matsuda Takashi Shimizu Naohisa Sakamoto Masahiro Fujita Keiji Onishi Eduardo C. Inacio Shun Ito Fumiyoshi Shoji Kenji Ono A Study on Open Source Software for Large-Scale Data Visualization on SPARC64fx based HPC Systems. 278-288 2018 HPC Asia https://doi.org/10.1145/3149457.3155323 conf/hpcasia/2018 db/conf/hpcasia/hpcasia2018.html#NonakaMSSFOIISO18 Genki Sugimoto Masahiro Fujita Yuto Mano Tetsushi Ohki Masakatsu Nishigaki Micro Disposable Biometric Authentication: An Application Using Fingernail Minute Textures for Nonsensitive Services. 68-73 2018 ICBSP https://doi.org/10.1145/3288200.3288209 conf/icbsp/2018 db/conf/icbsp/icbsp2018.html#SugimotoFMON18 Shuhei Maeda Satoru Ohshita Kazuma Furutani Yuto Yakubo Takahiko Ishizu Tomoaki Atsumi Yoshinori Ando Daisuke Matsubayashi Kiyoshi Kato Takashi Okuda Masahiro Fujita Shunpei Yamazaki A 20ns-write 45ns-read and 1014-cycle endurance memory module composed of 60nm crystalline oxide semiconductor transistors. 484-486 2018 ISSCC https://doi.org/10.1109/ISSCC.2018.8310395 conf/isscc/2018 db/conf/isscc/isscc2018.html#MaedaOFYIAAMKOF18 Jorji Nonaka Kenji Ono Naohisa Sakamoto Kengo Hayashi Motohiko Matsuda Fumiyoshi Shoji Kentaro Oku Masahiro Fujita Kazuma Hatta A Large Data Visualization Framework for SPARC64 fx HPC Systems - Case Study: K Computer Operational Environment -. 108-109 2018 LDAV https://doi.org/10.1109/LDAV.2018.8739214 conf/ldav/2018 db/conf/ldav/ldav2018.html#NonakaOSHMSOFH18

Tatsuya Onuki Wataru Uesugi Atsuo Isobe Yoshinori Ando Satoru Okamoto Kiyoshi Kato Tri Rung Yew J. Y. Wu Chi Chang Shuai Shao Hui Wu James Myers Klaus Doppler Masahiro Fujita Shunpei Yamazaki Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS. 925-932 2017 52 IEEE J. Solid State Circuits 4 https://doi.org/10.1109/JSSC.2016.2632303 db/journals/jssc/jssc52.html#OnukiUIAOKYWSWM17

Ayane Sano Masahiro Fujita Masakatsu Nishigaki Directcha-maze: A Study of CAPTCHA Configuration with Machine Learning and Brute-Force Attack Defensibility Along with User Convenience Consideration. 489-501 2017 BWCCA https://doi.org/10.1007/978-3-319-69811-3_45 conf/bwcca/2017 db/conf/bwcca/bwcca2017.html#SanoFN17 Ryohei Banno Jingyu Sun Masahiro Fujita Susumu Takeuchi Kazuyuki Shudo Dissemination of edge-heavy data on heterogeneous MQTT brokers. 5-11 2017 CloudNet https://doi.org/10.1109/CloudNet.2017.8071523 conf/cloudnet/2017 db/conf/cloudnet/cloudnet2017.html#BannoSFTS17 Shintaro Ishihara Masahiro Fujita Toyokazu Akiyama DNetSpec: A Distributed Network Testing Toolset for Middleware Developers. 1-6 2017 COMPSAC (2) https://doi.org/10.1109/COMPSAC.2017.111 https://doi.ieeecomputersociety.org/10.1109/COMPSAC.2017.111 conf/compsac/2017-2 db/conf/compsac/compsac2017-2.html#IshiharaMA17 Masahiro Fujita An approach to approximate computing: Logic transformations for one-minterm changes in specification. 91-94 2017 HLDVT https://doi.org/10.1109/HLDVT.2017.8167469 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2017.8167469 conf/hldvt/2017 db/conf/hldvt/hldvt2017.html#Fujita17 Jorji Nonaka Naohisa Sakamoto Takashi Shimizu Masahiro Fujita Kenji Ono Koji Koyamada Distributed Particle-Based Rendering Framework for Large Data Visualization on HPC Environments. 300-307 2017 HPCS https://doi.org/10.1109/HPCS.2017.54 conf/ieeehpcs/2017 db/conf/ieeehpcs/ieeehpcs2017.html#NonakaSSFOK17 Sahand Salamat Mehrnaz Ahmadi Bijan Alizadeh Masahiro Fujita Systematic approximate logic optimization using don't care conditions. 419-425 2017 ISQED https://doi.org/10.1109/ISQED.2017.7918352 conf/isqed/2017 db/conf/isqed/isqed2017.html#SalamatAAF17 Qinhao Wang Yusuke Kimura Masahiro Fujita Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs. 432-437 2017 ISQED https://doi.org/10.1109/ISQED.2017.7918354 conf/isqed/2017 db/conf/isqed/isqed2017.html#WangKF17 Kohei Mukaiyama Masahiro Fujita Takeharu Shirai Shinya Kobayashi Masakatsu Nishigaki Slyware Prevention: Threat of Websites Inducing Accidental Taps and Countermeasures. 539-552 2017 NBiS https://doi.org/10.1007/978-3-319-65521-5_47 conf/nbis/2017 db/conf/nbis/nbis2017.html#MukaiyamaFSKN17 Masahiro Fujita Yusuke Kimura Qinhao Wang Template based synthesis for high performance computing. 1-6 2017 VLSI-SoC https://doi.org/10.1109/VLSI-SoC.2017.8203492 conf/vlsi/2017soc db/conf/vlsi/vlsisoc2017.html#FujitaKW17 Payman Behnam Bijan Alizadeh Sajjad Taheri Masahiro Fujita Formally analyzing fault tolerance in datapath designs using equivalence checking. 133-138 2016 ASP-DAC https://doi.org/10.1109/ASPDAC.2016.7428001 conf/aspdac/2016 db/conf/aspdac/aspdac2016.html#BehnamATF16 Masahiro Fujita Synthesizing and Completely Testing Hardware Based on Templates Through Small Numbers of Test Patterns. 3-10 2016 ATVA https://doi.org/10.1007/978-3-319-46520-3_1 conf/atva/2016 db/conf/atva/atva2016.html#Fujita16 Takashi Tsuchiya Masahiro Fujita Kenta Takahashi Takehisa Kato Fumihiko Magata Yoshimi Teshigawara Ryôichi Sasaki Masakatsu Nishigaki Secure Communication Protocol Between a Human and a Bank Server for Preventing Man-in-the-Browser Attacks. 77-88 2016 HCI (20) https://doi.org/10.1007/978-3-319-39381-0_8 conf/hci/2016-20 db/conf/hci/hci2016-20.html#TsuchiyaFTKMTSN16 Masahiro Fujita Mako Yamada Masakatsu Nishigaki Implementation and Initial Evaluation of Game in Which Password Enhancement Factor is Embedded. 476-481 2016 HCI (26) https://doi.org/10.1007/978-3-319-40548-3_79 conf/hci/2016-26 db/conf/hci/hci2016-26.html#FujitaYN16 Yusuke Kimura Masahiro Fujita Specification by existing design plus use-cases. 40-45 2016 HLDVT https://doi.org/10.1109/HLDVT.2016.7748253 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2016.7748253 conf/hldvt/2016 db/conf/hldvt/hldvt2016.html#KimuraF16 Qinhao Wang Yusuke Kimura Masahiro Fujita Automatically adjusting system level designs after RTL/gate-level ECO. 108-112 2016 HLDVT https://doi.org/10.1109/HLDVT.2016.7748263 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2016.7748263 conf/hldvt/2016 db/conf/hldvt/hldvt2016.html#WangKF16 Masahiro Fujita Yuto Mano Takuya Kaneko Kenta Takahashi Masakatsu Nishigaki A Micro Biometric Authentication Mechanism Considering Minute Patterns of the Human Body: A Proposal and the First Attempt. 159-164 2016 NBiS https://doi.org/10.1109/NBiS.2016.13 https://doi.ieeecomputersociety.org/10.1109/NBiS.2016.13 conf/nbis/2016 db/conf/nbis/nbis2016.html#FujitaMKTN16 Takeharu Shirai Masahiro Fujita Daisuke Arai Tomohiko Ogishi Masakatsu Nishigaki Study on relationship between user awareness and QoE in communication delay on smartphones. 573-580 2016 PST https://doi.org/10.1109/PST.2016.7907019 conf/pst/2016 db/conf/pst/pst2016.html#ShiraiFAON16 Ayane Sano Masahiro Fujita Masakatsu Nishigaki Directcha: A proposal of spatiometric mental rotation CAPTCHA. 585-592 2016 PST https://doi.org/10.1109/PST.2016.7907021 conf/pst/2016 db/conf/pst/pst2016.html#SanoFN16 Eri Takane Kenjiro Tadakuma Masahiro Fujita Hirone Komatsu Akito Nomura Tomoya Ichimura Tomonari Yamamoto Yuichi Ambe Masashi Konyo Satoshi Tadokoro Two axes orthogonal drive transmission for omnidirectional crawler with surface contact. 378-383 2016 SSRR https://doi.org/10.1109/SSRR.2016.7784330 conf/ssrr/2016 db/conf/ssrr/ssrr2016.html#TakaneTFKNIYAKT16 Masahiro Fujita Kenjiro Tadakuma Eri Takane Tomoya Ichimura Hirone Komatsu Akito Nomura Masashi Konyo Satoshi Tadokoro Variable inner volume mechanism for soft and robust gripping - Improvement of gripping performance for large-object gripping. 390-395 2016 SSRR https://doi.org/10.1109/SSRR.2016.7784332 conf/ssrr/2016 db/conf/ssrr/ssrr2016.html#FujitaTTIKNKT16 Tatsuya Onuki Wataru Uesugi Hikaru Tamura Atsuo Isobe Yoshinori Ando Satoru Okamoto Kiyoshi Kato Tri Rung Yew Chen Bin Lin J. Y. Wu Chi Chang Shuai Shao Hui Wu James Myers Klaus Doppler Masahiro Fujita Shunpei Yamazaki Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS. 1-2 2016 VLSI Circuits https://doi.org/10.1109/VLSIC.2016.7573504 conf/vlsic/2016 db/conf/vlsic/vlsic2016.html#OnukiUTIAOKYLWS16

Masahiro Fujita Osamu Koike Yukio Yamaguchi Direct simulation of drying colloidal suspension on substrate using immersed free surface model. 421-448 2015 281 J. Comput. Phys. https://doi.org/10.1016/j.jcp.2014.10.042 db/journals/jcphy/jcphy281.html#FujitaKY15

Takeshi Aoki Yuki Okamoto Takashi Nakagawa Munehiro Kozuma Yoshiyuki Kurokawa Takayuki Ikeda Naoto Yamade Yutaka Okazaki Hidekazu Miyairi Masahiro Fujita Jun Koyama Shunpei Yamazaki Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register. 2199-2211 2015 50 IEEE J. Solid State Circuits 9 https://doi.org/10.1109/JSSC.2015.2438824 db/journals/jssc/jssc50.html#AokiONKKIYOMFKY15

Masahiro Fujita Toward Unification of Synthesis and Verification in Topologically Constrained Logic Design. 2052-2060 2015 103 Proc. IEEE 11 https://doi.org/10.1109/JPROC.2015.2476472 db/journals/pieee/pieee103.html#Fujita15

Samaneh Ghandali Bijan Alizadeh Masahiro Fujita Zainalabedin Navabi Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. 1579-1593 2015 64 IEEE Trans. Computers 6 https://doi.org/10.1109/TC.2014.2345395 http://doi.ieeecomputersociety.org/10.1109/TC.2014.2345395 db/journals/tc/tc64.html#GhandaliAFN15

Yuki Okamoto Takashi Nakagawa Takeshi Aoki Masataka Ikeda Munehiro Kozuma Takeshi Osada Yoshiyuki Kurokawa Takayuki Ikeda Naoto Yamade Yutaka Okazaki Hidekazu Miyairi Masahiro Fujita Jun Koyama Shunpei Yamazaki A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology. 422-434 2015 23 IEEE Trans. Very Large Scale Integr. Syst. 3 https://doi.org/10.1109/TVLSI.2014.2316871 db/journals/tvlsi/tvlsi23.html#OkamotoNAIKOKIY15

Masahiro Fujita Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification. 31-36 2015 ATS https://doi.org/10.1109/ATS.2015.13 https://doi.ieeecomputersociety.org/10.1109/ATS.2015.13 conf/ats/2015 db/conf/ats/ats2015.html#Fujita15 Masahiro Fujita On Implementation of LUT with Large Numbers of Inputs (Abstract Only). 277 2015 FPGA https://doi.org/10.1145/2684746.2689107 https://www.wikidata.org/entity/Q130992422 conf/fpga/2015 db/conf/fpga/fpga2015.html#Fujita15 Masahiro Fujita Yuki Ikeya Junya Kani Masakatsu Nishigaki Chimera CAPTCHA: A Proposal of CAPTCHA Using Strangeness in Merged Objects. 48-58 2015 HCI (22) https://doi.org/10.1007/978-3-319-20376-8_5 conf/hci/2015-22 db/conf/hci/hci2015-22.html#FujitaIKN15 Masahiro Fujita Automatic identification of assertions and invariants with small numbers of test vectors. 463-466 2015 ICCD https://doi.org/10.1109/ICCD.2015.7357149 https://doi.ieeecomputersociety.org/10.1109/ICCD.2015.7357149 conf/iccd/2015 db/conf/iccd/iccd2015.html#Fujita15 Jorji Nonaka Kenji Ono Masahiro Fujita 234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes. 421-428 2015 HPCS https://doi.org/10.1109/HPCSim.2015.7237071 conf/ieeehpcs/2015 db/conf/ieeehpcs/ieeehpcs2015.html#NonakaOF15 Masahiro Fujita Naoki Taguchi Kentaro Iwata Alan Mishchenko Incremental ATPG methods for multiple faults under multiple fault models. 177-180 2015 ISQED https://doi.org/10.1109/ISQED.2015.7085420 conf/isqed/2015 db/conf/isqed/isqed2015.html#FujitaTIM15 Takanori Matsuzaki Tatsuya Onuki Shuhei Nagatsuka Hiroki Inoue Takahiko Ishizu Yoshinori Ieda Naoto Yamade Hidekazu Miyairi Masayuki Sakakura Tomoaki Atsumi Yutaka Shionoiri Kiyoshi Kato Takashi Okuda Yoshitaka Yamamoto Masahiro Fujita Jun Koyama Shunpei Yamazaki 16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using Vt, cancel write method. 1-3 2015 ISSCC https://doi.org/10.1109/ISSCC.2015.7063048 conf/isscc/2015 db/conf/isscc/isscc2015.html#MatsuzakiONIIIY15 Sriram Karunagaran Karuna P. Sahoo Masahiro Fujita Hardware in loop testing of an insulin pump. 1-8 2015 ITC https://doi.org/10.1109/TEST.2015.7342416 conf/itc/2015 db/conf/itc/itc2015.html#KarunagaranSF15 Masahiro Fujita Logic analysis and optimization with quick identification of invariants through one time frame analysis. 102-107 2015 MEMOCODE https://doi.org/10.1109/MEMCOD.2015.7340476 https://www.wikidata.org/entity/Q130884229 conf/memocode/2015 db/conf/memocode/memocode2015.html#Fujita15 Masahiro Fujita Mako Yamada Shiori Arimura Yuki Ikeya Masakatsu Nishigaki An Attempt to Memorize Strong Passwords while Playing Games. 264-268 2015 NBiS https://doi.org/10.1109/NBiS.2015.41 https://doi.ieeecomputersociety.org/10.1109/NBiS.2015.41 conf/nbis/2015 db/conf/nbis/nbis2015.html#FujitaYAIN15 Masahiro Fujita Christian Damsgaard Jensen Shiori Arimura Yuki Ikeya Masakatsu Nishigaki Physical trust-based persistent authentication. 186-190 2015 PST https://doi.org/10.1109/PST.2015.7232972 https://doi.ieeecomputersociety.org/10.1109/PST.2015.7232972 conf/pst/2015 db/conf/pst/pst2015.html#FujitaJAIN15 Masahiro Fujita Analysis and testing on delays with two time frames. 13-18 2015 VLSI-SoC https://doi.org/10.1109/VLSI-SoC.2015.7314384 conf/vlsi/2015soc db/conf/vlsi/vlsisoc2015.html#Fujita15 Masahiro Fujita Delay Testing Based on Multiple Faulty Behaviors. 87-108 2015 VLSI-SoC (Selected Papers) https://doi.org/10.1007/978-3-319-46097-0_5 conf/vlsi/2015socs db/conf/vlsi/vlsisoc2015s.html#Fujita15a Reza Sharafinejad Bijan Alizadeh Masahiro Fujita UPF-based formal verification of low power techniques in modern processors. 1-6 2015 VTS https://doi.org/10.1109/VTS.2015.7116288 https://doi.ieeecomputersociety.org/10.1109/VTS.2015.7116288 conf/vts/2015 db/conf/vts/vts2015.html#SharafinejadAF15

Hiroaki Yoshida Masayuki Wakizaka Shigeru Yamashita Masahiro Fujita An Energy-Efficient Patchable Accelerator and Its Design Methods. 2507-2517 2014 97-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 https://doi.org/10.1587/transfun.E97.A.2507 http://search.ieice.org/bin/summary.php?id=e97-a_12_2507 db/journals/ieicet/ieicet97a.html#YoshidaWYF14

Satoshi Jo Takeshi Matsumoto Masahiro Fujita SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. 46-55 2014 7 IPSJ Trans. Syst. LSI Des. Methodol. https://doi.org/10.2197/ipsjtsldm.7.46 db/journals/ipsj/ipsj7.html#JoMF14

Hikaru Tamura Kiyoshi Kato Takahiko Ishizu Wataru Uesugi Atsuo Isobe Naoaki Tsutsui Yasutaka Suzuki Yutaka Okazaki Yukio Maehashi Jun Koyama Yoshitaka Yamamoto Shunpei Yamazaki Masahiro Fujita James Myers Pekka Korpinen Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor. 42-53 2014 34 IEEE Micro 6 https://doi.org/10.1109/MM.2014.96 http://doi.ieeecomputersociety.org/10.1109/MM.2014.96 db/journals/micro/micro34.html#TamuraKIUITSOMKYYFMK14

Hikaru Tamura Kiyoshi Kato Takahiko Ishizu Tatsuya Onuki Wataru Uesugi Takuro Ohmaru Kazuaki Ohshima Hidetomo Kobayashi Seiichi Yoneda Atsuo Isobe Naoaki Tsutsui Suguru Hondo Yasutaka Suzuki Yutaka Okazaki Tomoaki Atsumi Yutaka Shionoiri Yukio Maehashi Gensuke Goto Masahiro Fujita James Myers Pekka Korpinen Jun Koyama Yoshitaka Yamamoto Shunpei Yamazaki Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating. 1-3 2014 COOL Chips https://doi.org/10.1109/CoolChips.2014.6842955 https://doi.ieeecomputersociety.org/10.1109/CoolChips.2014.6842955 conf/coolchips/2014 db/conf/coolchips/coolchips2014.html#TamuraKIOUOOKYI14 Somayeh Sadeghi Kohan Payman Behnam Bijan Alizadeh Masahiro Fujita Zainalabedin Navabi Improving polynomial datapath debugging with HEDs. 1-6 2014 ETS https://doi.org/10.1109/ETS.2014.6847797 conf/ets/2014 db/conf/ets/ets2014.html#KohanBAFN14 Yuki Ikeya Masahiro Fujita Junya Kani Yuta Yoneyama Masakatsu Nishigaki An Image-Based CAPTCHA Using Sophisticated Mental Rotation. 57-68 2014 HCI (24) https://doi.org/10.1007/978-3-319-07620-1_6 conf/hci/2014-24 db/conf/hci/hci2014-24.html#IkeyaFKYN14 Jorji Nonaka Kenji Ono Masahiro Fujita Multi-step image compositing for massively parallel rendering. 627-634 2014 HPCS https://doi.org/10.1109/HPCSim.2014.6903746 conf/hpcs/2014 db/conf/hpcs/hpcs2014.html#NonakaOF14 Samaneh Ghandali Bijan Alizadeh Masahiro Fujita Zainalabedin Navabi RTL datapath optimization using system-level transformations. 309-316 2014 ISQED https://doi.org/10.1109/ISQED.2014.6783341 conf/isqed/2014 db/conf/isqed/isqed2014.html#GhandaliAFN14 Takeshi Aoki Yuki Okamoto Takashi Nakagawa Masataka Ikeda Munehiro Kozuma Takeshi Osada Yoshiyuki Kurokawa Takayuki Ikeda Naoto Yamade Yutaka Okazaki Hidekazu Miyairi Masahiro Fujita Jun Koyama Shunpei Yamazaki 30.9 Normally-off computing with crystalline InGaZnO-based FPGA. 502-503 2014 ISSCC https://doi.org/10.1109/ISSCC.2014.6757531 conf/isscc/2014 db/conf/isscc/isscc2014.html#AokiONIKOKIYOMF14 Masahiro Fujita Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults. 273-277 2014 ISVLSI https://doi.org/10.1109/ISVLSI.2014.116 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2014.116 conf/isvlsi/2014 db/conf/isvlsi/isvlsi2014.html#Fujita14 Masahiro Fujita Alan Mishchenko Efficient SAT-based ATPG techniques for all multiple stuck-at faults. 1-10 2014 ITC https://doi.org/10.1109/TEST.2014.7035351 https://doi.ieeecomputersociety.org/10.1109/TEST.2014.7035351 conf/itc/2014 db/conf/itc/itc2014.html#FujitaM14 Shiori Arimura Masahiro Fujita Shinya Kobayashi Junya Kani Masakatsu Nishigaki Akira Shiba i/k-Contact: A context-aware user authentication using physical social trust. 407-413 2014 PST https://doi.org/10.1109/PST.2014.6890968 https://doi.ieeecomputersociety.org/10.1109/PST.2014.6890968 conf/pst/2014 db/conf/pst/pst2014.html#ArimuraFKKNS14 Sriram Karunagaran Karuna P. Sahoo Jayaraj Poroor Masahiro Fujita MAESTRO: A time-driven embedded testbed Architecture with Event-driven Synchronization. 237-248 2014 RTAS https://doi.org/10.1109/RTAS.2014.6926006 https://doi.ieeecomputersociety.org/10.1109/RTAS.2014.6926006 conf/rtas/2014 db/conf/rtas/rtas2014.html#KarunagaranSPF14 Masahiro Fujita Alan Mishchenko Logic synthesis and verification on fixed topology. 1-6 2014 VLSI-SoC https://doi.org/10.1109/VLSI-SoC.2014.7004155 conf/vlsi/2014soc db/conf/vlsi/vlsisoc2014.html#FujitaM14 Atsuo Isobe Hikaru Tamura Kiyoshi Kato Takuro Ohmaru Wataru Uesugi Takahiko Ishizu Tatsuya Onuki Kazuaki Ohshima Takanori Matsuzaki Atsushi Hirose Yasutaka Suzuki Naoaki Tsutsui Tomoaki Atsumi Yutaka Shionoiri Gensuke Goto Jun Koyama Masahiro Fujita Shunpei Yamazaki A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor. 1-2 2014 VLSIC https://doi.org/10.1109/VLSIC.2014.6858379 conf/vlsic/2014 db/conf/vlsic/vlsic2014.html#IsobeTKOUIOOMHS14 Kosuke Oshima Takeshi Matsumoto Masahiro Fujita Hardware implementation of BLTL property checkers for acceleration of statistical model checking. 670-676 2013 ICCAD https://doi.org/10.1109/ICCAD.2013.6691187 http://dl.acm.org/citation.cfm?id=2561959 conf/iccad/2013 db/conf/iccad/iccad2013.html#OshimaMF13 Masahiro Fujita Satoshi Jo Shohei Ono Takeshi Matsumoto Partial synthesis through sampling with and without specification. 787-794 2013 ICCAD https://doi.org/10.1109/ICCAD.2013.6691203 http://dl.acm.org/citation.cfm?id=2561979 conf/iccad/2013 db/conf/iccad/iccad2013.html#FujitaJOM13 Kosuke Oshima Takeshi Matsumoto Masahiro Fujita Debugging Methods Through Identification of Appropriate Functions for Internal Gates. 1-22 2013 VLSI-SoC (Selected Papers) https://doi.org/10.1007/978-3-319-23799-2_1 conf/vlsi/2013socs db/conf/vlsi/vlsisoc2013s.html#OshimaMF13a Kosuke Oshima Takeshi Matsumoto Masahiro Fujita A debugging method for gate level circuit designs by introducing programmability. 78-83 2013 VLSI-SoC https://doi.org/10.1109/VLSI-SoC.2013.6673254 conf/vlsi/2013soc db/conf/vlsi/vlsisoc2013.html#OshimaMF13 Masahiro Fujita Takeshi Matsumoto Satoshi Jo FOF: Functionally Observable Fault and its ATPG techniques. 108-111 2013 VLSI-SoC https://doi.org/10.1109/VLSI-SoC.2013.6673259 conf/vlsi/2013soc db/conf/vlsi/vlsisoc2013.html#FujitaMJ13 Masahiro Fujita Hiroaki Yoshida Post-silicon patching for verification/debugging with high-level models and programmable logic. 232-237 2012 ASP-DAC https://doi.org/10.1109/ASPDAC.2012.6164951 conf/aspdac/2012 db/conf/aspdac/aspdac2012.html#FujitaY12 Yu-Shen Yang Andreas G. Veneris Nicola Nicolici Masahiro Fujita Automated data analysis techniques for a modern silicon debug environment. 298-303 2012 ASP-DAC https://doi.org/10.1109/ASPDAC.2012.6164963 conf/aspdac/2012 db/conf/aspdac/aspdac2012.html#YangVNF12 Hratch Mangassarian Hiroaki Yoshida Andreas G. Veneris Shigeru Yamashita Masahiro Fujita On error tolerance and Engineering Change with Partially Programmable Circuits. 695-700 2012 ASP-DAC https://doi.org/10.1109/ASPDAC.2012.6165045 conf/aspdac/2012 db/conf/aspdac/aspdac2012.html#MangassarianYVYF12 Satoshi Jo Takeshi Matsumoto Masahiro Fujita SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. 19-24 2012 Asian Test Symposium https://doi.org/10.1109/ATS.2012.55 https://doi.ieeecomputersociety.org/10.1109/ATS.2012.55 conf/ats/2012 db/conf/ats/ats2012.html#JoMF12 Masahiro Fujita Simulation-Based Analysis of Cyberphysical Systems. 485-492 2012 DSD https://doi.org/10.1109/DSD.2012.119 https://doi.ieeecomputersociety.org/10.1109/DSD.2012.119 conf/dsd/2012 db/conf/dsd/dsd2012.html#Fujita12 Masahiro Fujita Hiroaki Yoshida Post-silicon debugging targeting electrical errors with patchable controllers (abstract only). 271 2012 FPGA https://doi.org/10.1145/2145694.2145759 conf/fpga/2012 db/conf/fpga/fpga2012.html#FujitaY12 Bijan Alizadeh Masahiro Fujita A functional test generation technique for RTL datapaths. 64-70 2012 HLDVT https://doi.org/10.1109/HLDVT.2012.6418244 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2012.6418244 conf/hldvt/2012 db/conf/hldvt/hldvt2012.html#AlizadehF12 Masahiro Fujita Post-silicon verification and debugging with control flow traces and patchable hardware. 100-107 2012 HLDVT https://doi.org/10.1109/HLDVT.2012.6418250 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2012.6418250 conf/hldvt/2012 db/conf/hldvt/hldvt2012.html#Fujita12 Shohei Ono Takeshi Matsumoto Masahiro Fujita Automatic assertion extraction in gate-level simulation using GPGPUs. 522-523 2012 ICCD https://doi.org/10.1109/ICCD.2012.6378704 https://doi.ieeecomputersociety.org/10.1109/ICCD.2012.6378704 conf/iccd/2012 db/conf/iccd/iccd2012.html#OnoMF12 Samaneh Ghandali Bijan Alizadeh Zainalabedin Navabi Masahiro Fujita Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques. 65-74 2012 MEMOCODE https://doi.org/10.1109/MEMCOD.2012.6292301 conf/memocode/2012 db/conf/memocode/memocode2012.html#GhandaliANF12 Masahiro Fujita Future direction of digital content: 20th anniversary keynote talk. 1-2 2012 ACM Multimedia https://doi.org/10.1145/2393347.2393349 conf/mm/2012 db/conf/mm/mm2012.html#Fujita12 Koji Nakamaru Toru Matsuoka Masahiro Fujita Distance aware ray tracing for curves. 103 2012 SIGGRAPH Posters https://doi.org/10.1145/2342896.2343016 conf/siggraph/2012posters db/conf/siggraph/siggraph2012posters.html#NakamaruMF12 Takeshi Matsumoto Shohei Ono Masahiro Fujita An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence. 291-294 2012 VLSI-SoC https://doi.org/10.1109/VLSI-SoC.2012.6379049 conf/vlsi/2012soc db/conf/vlsi/vlsisoc2012.html#MatsumotoOF12

Görschwin Fey Masahiro Fujita Natasa Miskov-Zivanov Kaushik Roy 0001 Matteo Sonza Reorda Verifying Reliability (Dagstuhl Seminar 12341). 57-73 2012 2 Dagstuhl Reports 8 https://doi.org/10.4230/DagRep.2.8.57 db/journals/dagstuhl-reports/dagstuhl-reports2.html#FeyFMRR12

Tasuku Nishihara Takeshi Matsumoto Masahiro Fujita Multi-Level Bounded Model Checking with Symbolic Counterexamples. 696-705 2011 94-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 2 https://doi.org/10.1587/transfun.E94.A.696 http://search.ieice.org/bin/summary.php?id=e94-a_2_696 https://www.wikidata.org/entity/Q124804864 db/journals/ieicet/ieicet94a.html#NishiharaMF11

Yeonbok Lee Takeshi Matsumoto Masahiro Fujita An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging. 1519-1529 2011 94-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 7 https://doi.org/10.1587/transfun.E94.A.1519 http://search.ieice.org/bin/summary.php?id=e94-a_7_1519 db/journals/ieicet/ieicet94a.html#LeeMF11

Hiroaki Yoshida Masahiro Fujita Performance-Constrained Transistor Sizing for Different Cell Count Minimization. 1-11 2011 6 Inf. Media Technol. 1 https://doi.org/10.11185/imt.6.1 db/journals/imt/imt6.html#YoshidaF11 streams/journals/imt

Hiroaki Yoshida Masahiro Fujita Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability. 286-295 2011 6 Inf. Media Technol. 2 https://doi.org/10.11185/imt.6.286 db/journals/imt/imt6.html#YoshidaF11a streams/journals/imt

Hiroaki Yoshida Masahiro Fujita Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability. 70-79 2011 4 IPSJ Trans. Syst. LSI Des. Methodol. https://doi.org/10.2197/ipsjtsldm.4.70 db/journals/ipsj/ipsj4.html#YoshidaF11

Ratna Krishnamoorthy Saptarsi Das Keshavan Varadarajan Mythri Alle Masahiro Fujita Soumitra Kumar Nandy Ranjani Narayan Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture. 193-209 2011 4 IPSJ Trans. Syst. LSI Des. Methodol. https://doi.org/10.2197/ipsjtsldm.4.193 db/journals/ipsj/ipsj4.html#KrishnamoorthyDVAFNN11

Masahiro Fujita Accelerating Tsunami simulation with FPGA and GPU through automatic compilation. 79 2011 ACWR https://doi.org/10.1145/2185216.2185247 conf/acwr/2011 db/conf/acwr/acwr2011.html#Fujita11 Ratna Krishnamoorthy Keshavan Varadarajan Masahiro Fujita Mythri Alle S. K. Nandy 0001 Ranjani Narayan Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. 125-132 2011 ARC https://doi.org/10.1007/978-3-642-19475-7_15 conf/arc/2011 db/conf/arc/arc2011.html#KrishnamoorthyVFANN11 Masahiro Fujita Utilizing high level design information to speed up post-silicon debugging. 301-305 2011 ASP-DAC https://doi.org/10.1109/ASPDAC.2011.5722203 http://dl.acm.org/citation.cfm?id=1950883 conf/aspdac/2011 db/conf/aspdac/aspdac2011.html#Fujita11 Yeonbok Lee Takeshi Matsumoto Masahiro Fujita On-chip dynamic signal sequence slicing for efficient post-silicon debugging. 719-724 2011 ASP-DAC https://doi.org/10.1109/ASPDAC.2011.5722280 http://dl.acm.org/citation.cfm?id=1950953 conf/aspdac/2011 db/conf/aspdac/aspdac2011.html#LeeMF11 Masahiro Fujita High Level Verification and Its Use at Pos-Silicon Debugging and Patching. 464-469 2011 Asian Test Symposium https://doi.org/10.1109/ATS.2011.51 https://doi.ieeecomputersociety.org/10.1109/ATS.2011.51 conf/ats/2011 db/conf/ats/ats2011.html#Fujita11 Masahiro Fujita Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols. 43-50 2011 ATVA https://doi.org/10.1007/978-3-642-24372-1_4 conf/atva/2011 db/conf/atva/atva2011.html#Fujita11 Hiroaki Yoshida Masahiro Fujita An energy-efficient patchable accelerator for post-silicon engineering changes. 13-20 2011 CODES+ISSS https://doi.org/10.1145/2039370.2039376 conf/codes/2011 db/conf/codes/codes2011.html#YoshidaF11 Ratna Krishnamoorthy Masahiro Fujita Keshavan Varadarajan S. K. Nandy 0001 Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture. 1-5 2011 FPT https://doi.org/10.1109/FPT.2011.6132677 conf/fpt/2011 db/conf/fpt/fpt2011.html#KrishnamoorthyFVN11 Bijan Alizadeh Masahiro Fujita Modular equivalence verification of polynomial datapaths with multiple word-length operands. 9-16 2011 HLDVT https://doi.org/10.1109/HLDVT.2011.6114160 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2011.6114160 conf/hldvt/2011 db/conf/hldvt/hldvt2011.html#AlizadehF11 Hideo Tanida Masahiro Fujita Mukul R. Prasad Sreeranga P. Rajan Client-tier Validation of Dynamic Web Applications. 86-95 2011 ICSOFT (2) conf/icsoft/2011-2 db/conf/icsoft/icsoft2011-2.html#TanidaFPR11 Hideo Tanida Mukul R. Prasad Sreeranga P. Rajan Masahiro Fujita Automated System Testing of Dynamic Web Applications. 181-196 2011 ICSOFT (Selected Papers) https://doi.org/10.1007/978-3-642-36177-7_12 conf/icsoft/2011s db/conf/icsoft/icsoft2011s.html#TanidaPRF11 Bijan Alizadeh Masahiro Fujita Early case splitting and false path detection to improve high level ATPG techniques. 1463-1466 2011 ISCAS https://doi.org/10.1109/ISCAS.2011.5937850 conf/iscas/2011 db/conf/iscas/iscas2011.html#AlizadehF11 Bijan Alizadeh Masahiro Fujita Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. 297-302 2011 ISQED https://doi.org/10.1109/ISQED.2011.5770740 conf/isqed/2011 db/conf/isqed/isqed2011.html#AlizadehF11

Kenshu Seto Masahiro Fujita Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. 376-387 2010 5 Inf. Media Technol. 2 https://doi.org/10.11185/imt.5.376 db/journals/imt/imt5.html#SetoF10

Kenshu Seto Masahiro Fujita Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. 57-68 2010 3 IPSJ Trans. Syst. LSI Des. Methodol. https://doi.org/10.2197/ipsjtsldm.3.57 db/journals/ipsj/ipsj3.html#SetoF10

Takeshi Matsumoto Tasuku Nishihara Masahiro Fujita Performance Estimation with Automatic False-Path Detection for System-Level Designs. 69-80 2010 3 IPSJ Trans. Syst. LSI Des. Methodol. https://doi.org/10.2197/ipsjtsldm.3.69 db/journals/ipsj/ipsj3.html#MatsumotoNF10

Hiroaki Yoshida Masahiro Fujita Performance-Constrained Transistor Sizing for Different Cell Count Minimization. 252-262 2010 18 J. Inf. Process. https://doi.org/10.2197/ipsjjip.18.252 db/journals/jip/jip18.html#YoshidaF10

Masahiro Fujita Alan G. Mallinger Carlos A. Zarate Jr. Leah P. Dickstein Sami S. Zoghbi Victor W. Pike Yi Zhang Robert B. Innis Wayne C. Drevets Changes of brain phosphodiesterase 4 in major depression. S51 2010 52 NeuroImage Supplement-1 https://doi.org/10.1016/j.neuroimage.2010.04.232 db/journals/neuroimage/neuroimage52.html#FujitaMZDZPZID10

Bijan Alizadeh Mohammad Mirzaei Masahiro Fujita Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits. 737-748 2010 29 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/TCAD.2010.2043571 db/journals/tcad/tcad29.html#AlizadehMF10

Bijan Alizadeh Masahiro Fujita Modular Datapath Optimization and Verification Based on Modular-HED. 1422-1435 2010 29 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/TCAD.2010.2059271 db/journals/tcad/tcad29.html#AlizadehF10

Bijan Alizadeh Masahiro Fujita Guided gate-level ATPG for sequential circuits using a high-level test generation approach. 425-430 2010 ASP-DAC https://doi.org/10.1109/ASPDAC.2010.5419843 http://dl.acm.org/citation.cfm?id=1899824 conf/aspdac/2010 db/conf/aspdac/aspdac2010.html#AlizadehF10 Ratna Krishnamoorthy Keshavan Varadarajan Ganesh Garga Mythri Alle S. K. Nandy 0001 Ranjani Narayan Masahiro Fujita Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. 77-86 2010 CASES https://doi.org/10.1145/1878921.1878935 conf/cases/2010 db/conf/cases/cases2010.html#KrishnamoorthyVGANNF10 Bijan Alizadeh Masahiro Fujita A debugging method for repairing post-silicon bugs of high performance processors in the fields. 328-331 2010 FPT https://doi.org/10.1109/FPT.2010.5681434 conf/fpt/2010 db/conf/fpt/fpt2010.html#AlizadehF10 Finn Haedicke Bijan Alizadeh Görschwin Fey Masahiro Fujita Rolf Drechsler Polynomial datapath optimization using constraint solving and formal modelling. 756-761 2010 ICCAD https://doi.org/10.1109/ICCAD.2010.5654279 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2010.5654279 http://dl.acm.org/citation.cfm?id=2133589 https://www.wikidata.org/entity/Q59242630 conf/iccad/2010 db/conf/iccad/iccad2010.html#HaedickeAFFD10 Yeonbok Lee Takeshi Matsumoto Masahiro Fujita Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging. 402-408 2010 ICCD https://doi.org/10.1109/ICCD.2010.5647681 https://doi.ieeecomputersociety.org/10.1109/ICCD.2010.5647681 conf/iccd/2010 db/conf/iccd/iccd2010.html#LeeMF10 Masahiro Fujita Hideo Tanida Fei Gao Tasuku Nishihara Takeshi Matsumoto Synthesis and formal verification of on-chip protocol transducers through decomposed specification. 515-523 2010 ISQED https://doi.org/10.1109/ISQED.2010.5450526 conf/isqed/2010 db/conf/isqed/isqed2010.html#FujitaTGNM10 Guillermo Lopez Tomoki Tanemura Ryo Sato Takahiro Saeki Yoshikazu Hirai Koji Sugano Toshiyuki Tsuchiya Osamu Tabata Masahiro Fujita Mizuo Maeda DNA-grafted-polymer mediated self-assembly of micro components. 245-249 2010 NEMS https://doi.org/10.1109/NEMS.2010.5592199 conf/nems/2010 db/conf/nems/nems2010.html#LopezTSSHSTTFM10

Masahiro Fujita Intelligence Dynamics: a concept and preliminary experiments for open-ended learning agents. 248-271 2009 19 Auton. Agents Multi Agent Syst. 3 https://doi.org/10.1007/s10458-009-9076-y db/journals/aamas/aamas19.html#Fujita09

Anmol Mathur Masahiro Fujita Edmund M. Clarke Pascal Urard Functional Equivalence Verification Tools in High-Level Synthesis Flows. 88-95 2009 26 IEEE Des. Test Comput. 4 https://doi.org/10.1109/MDT.2009.79 http://doi.ieeecomputersociety.org/10.1109/MDT.2009.79 db/journals/dt/dt26.html#MathurFCU09

Tasuku Nishihara Takeshi Matsumoto Masahiro Fujita Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath. 972-984 2009 92-D IEICE Trans. Inf. Syst. 5 https://doi.org/10.1587/transinf.E92.D.972 http://search.ieice.org/bin/summary.php?id=e92-d_5_972&category=D&year=2009&lang=E&abst= db/journals/ieicet/ieicet92d.html#NishiharaMF09

Bijan Alizadeh Masahiro Fujita A Unified Framework for Equivalence Verification of Datapath Oriented Applications. 985-994 2009 92-D IEICE Trans. Inf. Syst. 5 https://doi.org/10.1587/transinf.E92.D.985 http://search.ieice.org/bin/summary.php?id=e92-d_5_985&category=D&year=2009&lang=E&abst= db/journals/ieicet/ieicet92d.html#AlizadehF09

Shanghua Gao Hiroaki Yoshida Kenshu Seto Satoshi Komatsu Masahiro Fujita Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. 1464-1475 2009 92-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 6 https://doi.org/10.1587/transfun.E92.A.1464 http://search.ieice.org/bin/summary.php?id=e92-a_6_1464&category=A&year=2009&lang=E&abst= db/journals/ieicet/ieicet92a.html#GaoYSKF09

Masahiro Fujita Trends in Formal Verification Techniques for C-based Hardware Designs. 149-164 2009 4 Inf. Media Technol. 2 https://doi.org/10.11185/imt.4.149 db/journals/imt/imt4.html#Fujita09

Masahiro Fujita Trends in Formal Verification Techniques for C-based Hardware Designs. 2-17 2009 2 IPSJ Trans. Syst. LSI Des. Methodol. https://doi.org/10.2197/ipsjtsldm.2.2 db/journals/ipsj/ipsj2.html#Fujita09

Omid Sarbishei Mahmoud Tabandeh Bijan Alizadeh Masahiro Fujita A Formal Approach for Debugging Arithmetic Circuits. 742-754 2009 28 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/TCAD.2009.2013998 db/journals/tcad/tcad28.html#SarbisheiTAF09

Yeonbok Lee Tasuku Nishihara Takeshi Matsumoto Masahiro Fujita A Post-Silicon Debug Support Using High-Level Design Description. 137-142 2009 Asian Test Symposium https://doi.org/10.1109/ATS.2009.28 https://doi.ieeecomputersociety.org/10.1109/ATS.2009.28 conf/ats/2009 db/conf/ats/ats2009.html#LeeNMF09 Omid Sarbishei Bijan Alizadeh Masahiro Fujita Polynomial datapath optimization using partitioning and compensation heuristics. 931-936 2009 DAC https://doi.org/10.1145/1629911.1630151 conf/dac/2009 db/conf/dac/dac2009.html#SarbisheiAF09 Bijan Alizadeh Masahiro Fujita Modular arithmetic decision procedure with auto-correction mechanism. 138-145 2009 HLDVT https://doi.org/10.1109/HLDVT.2009.5340162 conf/hldvt/2009 db/conf/hldvt/hldvt2009.html#AlizadehF09 Bijan Alizadeh Masahiro Fujita Improved heuristics for finite word-length polynomial datapath optimization. 739-744 2009 ICCAD https://doi.org/10.1145/1687399.1687536 https://ieeexplore.ieee.org/document/5361213/ conf/iccad/2009 db/conf/iccad/iccad2009.html#AlizadehF09 Hiroaki Yoshida Masahiro Fujita Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences. 366-370 2009 ISQED https://doi.org/10.1109/ISQED.2009.4810322 https://doi.ieeecomputersociety.org/10.1109/ISQED.2009.4810322 conf/isqed/2009 db/conf/isqed/isqed2009.html#YoshidaF09 Omid Sarbishei Mahmoud Tabandeh Bijan Alizadeh Masahiro Fujita High-level optimization of integer multipliers over a finite bit-width with verification capabilities. 56-65 2009 MEMOCODE https://doi.org/10.1109/MEMCOD.2009.5185378 http://dl.acm.org/citation.cfm?id=1715766 conf/memocode/2009 db/conf/memocode/memocode2009.html#SarbisheiTAF09 Bernd Becker 0001 V. Bertacoo Rolf Drechsler Masahiro Fujita Algorithms and Applications for Next Generation SAT Solvers, 08.11. - 13.11.2009 Algorithms and Applications for Next Generation SAT Solvers 09461 2009 Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany Dagstuhl Seminar Proceedings db/conf/dagstuhl/P9461.html http://drops.dagstuhl.de/portals/09461/ Bernd Becker 0001 Valeria Bertacco Rolf Drechsler Masahiro Fujita 09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers. 2009 Algorithms and Applications for Next Generation SAT Solvers http://drops.dagstuhl.de/opus/volltexte/2010/2511/ conf/dagstuhl/2009P9461 db/conf/dagstuhl/P9461.html#BeckerBDF09 Masahiro Fujita Indradeep Ghosh Mukul R. Prasad Verification Techniques for System-Level Design. I-VIII, 1-240 Morgan Kaufmann 2008 The Morgan Kaufmann series in systems on silicon 978-0-12-370616-4 http://www.elsevier.com/wps/find/bookdescription.cws_home/712870/description#description

Jens-Steffen Gutmann Masaki Fukuchi Masahiro Fujita 3D Perception and Environment Map Generation for Humanoid Robot Navigation. 1117-1134 2008 27 Int. J. Robotics Res. 10 https://doi.org/10.1177/0278364908096316 db/journals/ijrr/ijrr27.html#GutmannFF08

Masahiro Fujita Kenshu Seto Thanyapat Sakunkonchak Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation. 57-82 2008 5 J. Satisf. Boolean Model. Comput. 1-4 https://doi.org/10.3233/sat190052 db/journals/jsat/jsat5.html#FujitaSS08

Görschwin Fey Satoshi Komatsu Yasuo Furukawa Masahiro Fujita Targeting Leakage Constraints during ATPG. 225-230 2008 ATS https://doi.org/10.1109/ATS.2008.14 https://doi.ieeecomputersociety.org/10.1109/ATS.2008.14 conf/ats/2008 db/conf/ats/ats2008.html#FeyKFF08 Yoshihisa Kojima Tasuku Nishihara Takeshi Matsumoto Masahiro Fujita An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs. 315-320 2008 ATS https://doi.org/10.1109/ATS.2008.62 https://doi.ieeecomputersociety.org/10.1109/ATS.2008.62 conf/ats/2008 db/conf/ats/ats2008.html#KojimaNMF08 Bijan Alizadeh Masahiro Fujita Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram. 697-704 2008 CSICC https://doi.org/10.1007/978-3-540-89985-3_85 conf/csicc/2008 db/conf/csicc/csicc2008.html#AlizadehF08 Hiroaki Yoshida Masahiro Fujita Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits. 1099-1102 2008 DATE https://doi.org/10.1109/DATE.2008.4484924 https://doi.ieeecomputersociety.org/10.1109/DATE.2008.4484924 https://doi.org/10.1145/1403375.1403639 conf/date/2008 db/conf/date/date2008.html#YoshidaF08 Tasuku Nishihara Takeshi Matsumoto Masahiro Fujita Multi-level Bounded Model Checking to detect bugs beyond the bound. 49-55 2008 HLDVT https://doi.org/10.1109/HLDVT.2008.4695874 conf/hldvt/2008 db/conf/hldvt/hldvt2008.html#NishiharaMF08 Taro Takahashi Toshimitsu Tsuboi Takeo Kishida Yasunori Kawanami Satoru Shimizu Masatsugu Iribe Tetsuharu Fukushima Masahiro Fujita Adaptive grasping by multi fingered hand with tactile sensor based on robust force and position control. 264-271 2008 ICRA https://doi.org/10.1109/ROBOT.2008.4543219 conf/icra/2008 db/conf/icra/icra2008.html#TakahashiTKKSIFF08 Masahiro Fujita Takeshi Matsumoto Hiroaki Yoshida A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams. 240-245 2008 ICSOFT (SE/MUSE/GSDCA) conf/icsoft/2008-2 db/conf/icsoft/icsoft2008-2.html#FujitaMY08 Ken'ichiro Nagasaka Atsushi Miyamoto Masakuni Nagano Hirokazu Shirado Tetsuharu Fukushima Masahiro Fujita Motion control of a virtual humanoid that can perform real physical interactions with a human. 2303-2310 2008 IROS https://doi.org/10.1109/IROS.2008.4650680 conf/iros/2008 db/conf/iros/iros2008.html#NagasakaMNSFF08 Omid Sarbishei Bijan Alizadeh Masahiro Fujita Arithmetic Circuits Verification without Looking for Internal Equivalences. 7-16 2008 MEMOCODE https://doi.org/10.1109/MEMCOD.2008.4547681 https://doi.ieeecomputersociety.org/10.1109/MEMCOD.2008.4547681 conf/memocode/2008 db/conf/memocode/memocode2008.html#SarbisheiAF08 Subash Shankar Masahiro Fujita Rule-Based Approaches for Equivalence Checking of SpecC Programs. 39-48 2008 MEMOCODE https://doi.org/10.1109/MEMCOD.2008.4547685 https://doi.ieeecomputersociety.org/10.1109/MEMCOD.2008.4547685 conf/memocode/2008 db/conf/memocode/memocode2008.html#ShankarF08 Kenshu Seto Masahiro Fujita Custom Instruction Generation with High-Level Synthesis. 14-19 2008 SASP https://doi.org/10.1109/SASP.2008.4570780 https://doi.ieeecomputersociety.org/10.1109/SASP.2008.4570780 conf/sasp/2008 db/conf/sasp/sasp2008.html#SetoF08

Masahiro Fujita Yukio Yamaguchi Multiscale simulation method for self-organization of nanoparticles in dense suspension. 108-120 2007 223 J. Comput. Phys. 1 https://doi.org/10.1016/j.jcp.2006.09.001 db/journals/jcphy/jcphy223.html#FujitaY07

Shunsuke Sasaki Tasuku Nishihara Daisuke Ando Masahiro Fujita Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph. 1972-2001 2007 13 J. Univers. Comput. Sci. 13 https://doi.org/10.3217/jucs-013-13-1972 db/journals/jucs/jucs13.html#SasakiNAF07

Shigeru Watanabe Kenshu Seto Yuji Ishikawa Satoshi Komatsu Masahiro Fujita Protocol Transducer Synthesis using Divide and Conquer approach. 280-285 2007 conf/aspdac/2007 ASP-DAC https://doi.org/10.1109/ASPDAC.2007.357999 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357999 http://dl.acm.org/citation.cfm?id=1323378 db/conf/aspdac/aspdac2007.html#WatanabeSIKF07 Bijan Alizadeh Masahiro Fujita Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. 129-144 2007 conf/atva/2007 ATVA https://doi.org/10.1007/978-3-540-75596-8_11 db/conf/atva/atva2007.html#AlizadehF07 Thanyapat Sakunkonchak Satoshi Komatsu Masahiro Fujita Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction. 553-563 2007 conf/atva/2007 ATVA https://doi.org/10.1007/978-3-540-75596-8_40 db/conf/atva/atva2007.html#SakunkonchakKF07 Takeshi Matsumoto Daisuke Ando Tasuku Nishihara Masahiro Fujita Development and Verification of a Collaborative Printing Environment. 99-108 2007 conf/c5/2007 C5 https://doi.org/10.1109/C5.2007.8 https://doi.ieeecomputersociety.org/10.1109/C5.2007.8 db/conf/c5/c5-2007.html#MatsumotoANF07 Bijan Alizadeh Masahiro Fujita A novel formal approach to generate high-level test vectors without ILP and SAT solvers. 97-104 2007 HLDVT https://doi.org/10.1109/HLDVT.2007.4392794 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2007.4392794 conf/hldvt/2007 db/conf/hldvt/hldvt2007.html#AlizadehF07 Shanghua Gao Kenshu Seto Satoshi Komatsu Masahiro Fujita Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. 121-134 2007 conf/iess/2007 IESS https://doi.org/10.1007/978-0-387-72258-0_11 db/conf/iess/iess2007.html#GaoSKF07 Makoto Aso Masahiro Fujita Keitaro Niki Lateral State Prediction for Automated Steering using Reliability-Weighted Measurements from Multiple Sensors. 461-466 2007 ITSC https://doi.org/10.1109/ITSC.2007.4357643 conf/itsc/2007 db/conf/itsc/itsc2007.html#AsoFN07 Satoshi Komatsu Kazuyoshi Takagi Masahiro Fujita Kunihiro Asada VLSI CAD Education and Exercise Course with Public Domain Tools. 111-112 2007 MSE https://doi.org/10.1109/MSE.2007.90 https://doi.ieeecomputersociety.org/10.1109/MSE.2007.90 conf/mse/2007 db/conf/mse/mse2007.html#KomatsuTFA07

Yu Liu Satoshi Komatsu Masahiro Fujita Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment. 1018-1026 2006 89-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 4 https://doi.org/10.1093/ietfec/e89-a.4.1018 db/journals/ieicet/ieicet89a.html#LiuKF06

Thanyapat Sakunkonchak Satoshi Komatsu Masahiro Fujita Synchronization Verification in System-Level Design with ILP Solvers. 3387-3396 2006 89-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 https://doi.org/10.1093/ietfec/e89-a.12.3387 db/journals/ieicet/ieicet89a.html#SakunkonchakKF06

Yu Liu Satoshi Komatsu Masahiro Fujita The AMS Extension to System Level Design Language - SpecC. 3397-3407 2006 89-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 https://doi.org/10.1093/ietfec/e89-a.12.3397 db/journals/ieicet/ieicet89a.html#LiuKF06a

David W. Currie Xiushan Feng Masahiro Fujita Alan J. Hu Mark Kwan Sreeranga P. Rajan Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions. 61-91 2006 34 Int. J. Parallel Program. 1 https://doi.org/10.1007/s10766-005-0004-8 db/journals/ijpp/ijpp34.html#CurrieFFHKR06

Ken Matsui Masahiro Fujita Object-oriented analysis and specification for HW/SW co-design with UML diagrams. 38-43 2006 conf/acst/2006 ACST db/conf/acst/acst2006.html#MatsuiF06 Masahiro Fujita Tasuku Nishihara Daisuke Ando System LSI distributed collaborative design environment for both designers and CAD developers/engineers. 175-183 2006 conf/c5/2006 C5 https://doi.org/10.1109/C5.2006.36 https://doi.ieeecomputersociety.org/10.1109/C5.2006.36 db/conf/c5/c5-2006.html#FujitaNA06 Shota Watanabe Yuji Ishikawa Kenshu Seto Satoshi Komatsu Masahiro Fujita Dynamically reconfigurable protocol transducer. 341-344 2006 FPT https://doi.org/10.1109/FPT.2006.270343 conf/fpt/2006 db/conf/fpt/fpt2006.html#WatanabeISKF06 Tasuku Nishihara Takeshi Matsumoto Masahiro Fujita Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis. 162-169 2006 HLDVT https://doi.org/10.1109/HLDVT.2006.319984 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2006.319984 conf/hldvt/2006 db/conf/hldvt/hldvt2006.html#NishiharaMF06 Satoshi Komatsu Masahiro Fujita An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme. 2006 conf/iscas/2006 ISCAS https://doi.org/10.1109/ISCAS.2006.1692937 db/conf/iscas/iscas2006.html#KomatsuF06 Takeshi Matsumoto Hiroshi Saito Masahiro Fujita Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs. 370-375 2006 conf/isqed/2006 ISQED https://doi.org/10.1109/ISQED.2006.61 https://doi.ieeecomputersociety.org/10.1109/ISQED.2006.61 https://www.wikidata.org/entity/Q131125886 db/conf/isqed/isqed2006.html#MatsumotoSF06 Masahiro Fujita Subash Shankar Sasaki Shunsuke Equivalence checking: a rule-based approach. 197 2006 conf/memocode/2006 MEMOCODE https://doi.org/10.1109/MEMCOD.2006.1695926 https://doi.ieeecomputersociety.org/10.1109/MEMCOD.2006.1695926 http://dl.acm.org/citation.cfm?id=2674333 db/conf/memocode/memocode2006.html#FujitaSS06 Anmol Mathur Masahiro Fujita M. Balakrishnan Raj S. Mitra Sequential Equivalence Checking. 18-19 2006 conf/vlsid/2006 VLSI Design https://doi.org/10.1109/VLSID.2006.145 https://doi.ieeecomputersociety.org/10.1109/VLSID.2006.145 db/conf/vlsid/vlsid2006.html#MathurFBM06

Satoshi Komatsu Masahiro Fujita Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications. 3282-3289 2005 88-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 https://doi.org/10.1093/ietfec/e88-a.12.3282 db/journals/ieicet/ieicet88a.html#KomatsuF05

Takeshi Matsumoto Hiroshi Saito Masahiro Fujita An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences. 3315-3323 2005 88-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 https://doi.org/10.1093/ietfec/e88-a.12.3315 db/journals/ieicet/ieicet88a.html#MatsumotoSF05

Masahiro Fujita Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. 610-626 2005 10 ACM Trans. Design Autom. Electr. Syst. 4 https://doi.org/10.1145/1109118.1109121 db/journals/todaes/todaes10.html#Fujita05

Gregory S. Hornby Seiichi Takamura Takashi Yamamoto Masahiro Fujita Autonomous evolution of dynamic gaits with two quadruped robots. 402-410 2005 21 IEEE Trans. Robotics 3 https://doi.org/10.1109/TRO.2004.839222 db/journals/trob/trob21.html#HornbyTYF05

Masahiro Fujita Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. 340-344 2005 conf/charme/2005 CHARME https://doi.org/10.1007/11560548_27 db/conf/charme/charme2005.html#Fujita05 Yosuke Bando Takahiro Saito Masahiro Fujita Hexagonal storage scheme for interleaved frame buffers and textures. 33-40 2005 conf/egh/2005 Graphics Hardware https://doi.org/10.2312/EGGH/EGGH05/033-040 https://doi.org/10.1145/1071866.1071872 db/conf/egh/egh2005.html#BandoSF05 Yu Liu Satoshi Komatsu Masahiro Fujita AMS Extensions for Timed/Untimed System-Level Design Language. 77-81 2005 FDL http://www.ecsi-association.org/ecsi/main.asp?l1=library&fn=def&id=422 conf/fdl/2005 db/conf/fdl/fdl2005.html#LiuKF05 Shanghua Gao Kenshu Seto Satoshi Komatsu Masahiro Fujita Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. 137-144 2005 conf/fpt/2005 FPT db/conf/fpt/fpt2005.html#GaoSKF05 Yu Liu Thanyapat Sakunkonchak Satoshi Komatsu Masahiro Fujita System level design language extensions for timed/untimed digital-analog combined system design. 130-133 2005 conf/glvlsi/2005 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1057661.1057693 db/conf/glvlsi/glvlsi2005.html#LiuSKF05 Jens-Steffen Gutmann Masaki Fukuchi Masahiro Fujita A modular architecture for humanoid robot navigation. 26-31 2005 Humanoids https://doi.org/10.1109/ICHR.2005.1573540 conf/humanoids/2005 db/conf/humanoids/humanoids2005.html#GutmannFF05 Jens-Steffen Gutmann Masaki Fukuchi Masahiro Fujita A Floor and Obstacle Height Map for 3D Navigation of a Humanoid Robot. 1066-1071 2005 conf/icra/2005 ICRA db/conf/icra/icra2005.html#GutmannFF05 https://doi.org/10.1109/ROBOT.2005.1570257 Jens-Steffen Gutmann Masaki Fukuchi Masahiro Fujita Real-Time Path Planning for Humanoid Robot Navigation. 1232-1237 2005 conf/ijcai/2005 IJCAI http://ijcai.org/Proceedings/05/Papers/0974.pdf db/conf/ijcai/ijcai2005.html#GutmannFF05 Masahiro Fujita Shunsuke Sasaki Ken Matsui Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse. 318-325 2005 conf/iri/2005 IRI https://doi.org/10.1109/IRI-05.2005.1506493 db/conf/iri/iri2005.html#FujitaSM05 Thanyapat Sakunkonchak Satoshi Komatsu Masahiro Fujita Synchronization verification in system-level design with ILP solvers. 121-130 2005 conf/memocode/2005 MEMOCODE https://doi.org/10.1109/MEMCOD.2005.1487902 https://doi.ieeecomputersociety.org/10.1109/MEMCOD.2005.1487902 http://dl.acm.org/citation.cfm?id=1322151 db/conf/memocode/memocode2005.html#SakunkonchakKF05 Masahiro Fujita Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL. 241-242 2005 conf/memocode/2005 MEMOCODE https://doi.org/10.1109/MEMCOD.2005.1487923 https://doi.ieeecomputersociety.org/10.1109/MEMCOD.2005.1487923 http://dl.acm.org/citation.cfm?id=1322165 db/conf/memocode/memocode2005.html#Fujita05 Shunsuke Sasaki Tasuku Nishihara Masahiro Fujita Slicing-based Hardware/Software Co-design Methodology From Functional Specifications. 265-280 2005 conf/fsen/2005 FSEN https://doi.org/10.1016/j.entcs.2005.12.071 db/journals/entcs/entcs159.html#SasakiNF06

Masahiro Fujita On activating human communications with pet-type robot AIBO. 1804-1813 2004 92 Proc. IEEE 11 https://doi.org/10.1109/JPROC.2004.835364 db/journals/pieee/pieee92.html#Fujita04

Masahiro Fujita Takashi Kanai Precomputed Radiance Transfer with Spatially-Varying Lighting Effects. 101-108 2004 conf/IEEEcgiv/2004 CGIV https://doi.org/10.1109/CGIV.2004.1323968 https://doi.ieeecomputersociety.org/10.1109/CGIV.2004.1323968 db/conf/IEEEcgiv/cgiv2004.html#FujitaK04 Masahiro Fujita On equivalence checking between behavioral and RTL descriptions. 179-184 2004 HLDVT https://doi.org/10.1109/HLDVT.2004.1431267 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2004.1431267 conf/hldvt/2004 db/conf/hldvt/hldvt2004.html#Fujita04 Tsutomu Sawada Tsuyoshi Takagi Yukiko Hoshino Masahiro Fujita Learning behavior selection through interaction based on emotionally grounded symbol concept. 450-469 2004 Humanoids https://doi.org/10.1109/ICHR.2004.1442137 conf/humanoids/2004 db/conf/humanoids/humanoids2004.html#SawadaTHF04 Yukiko Hoshino Tsuyoshi Takagi Ugo Di Profio Masahiro Fujita Behavior Description and Control using Behavior Module for Personal Robot. 4165-4171 2004 conf/icra/2004 ICRA https://doi.org/10.1109/ROBOT.2004.1308925 db/conf/icra/icra2004-4.html#HoshinoTPF04 Jens-Steffen Gutmann Masaki Fukuchi Masahiro Fujita Stair climbing for humanoid robots using stereo vision. 1407-1413 2004 IROS https://doi.org/10.1109/IROS.2004.1389593 conf/iros/2004 db/conf/iros/iros2004.html#GutmannFF04 Tsutomu Sawada Tsuyoshi Takagi Masahiro Fujita Behavior selection and motion modulation in emotionally grounded architecture for QRIO SDR-4XII. 2514-2519 2004 IROS https://doi.org/10.1109/IROS.2004.1389786 conf/iros/2004 db/conf/iros/iros2004.html#SawadaTF04 Fumihide Tanaka Kuniaki Noda Tsutomu Sawada Masahiro Fujita Associated Emotion and Its Expression in an Entertainment Robot QRIO. 499-504 https://doi.org/10.1007/978-3-540-28643-1_64 2004 conf/iwec/2004 ICEC db/conf/iwec/icec2004.html#TanakaNSF04 Indradeep Ghosh Rajarshi Mukherjee Mukul R. Prasad Masahiro Fujita High Level Design Validation: Current Practices and Future Directions. 9-11 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1260892 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260892 db/conf/vlsid/vlsid2004.html#GhoshMPF04 Masahiro Fujita Formal Verification of C Language Based VLSI Designs. 93- 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1260908 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260908 db/conf/vlsid/vlsid2004.html#Fujita04

Minoru Asada Oliver Obst Daniel Polani Brett Browning Andrea Bonarini Masahiro Fujita Thomas Christaller Tomoichi Takahashi Satoshi Tadokoro Elizabeth Sklar Gal A. Kaminka An Overview of RoboCup-2002 Fukuoka/Busan. 21-40 2003 24 AI Mag. 2 db/journals/aim/aim24.html#AsadaOPBBFCTTSK03 https://doi.org/10.1609/aimag.v24i2.1700

Satoshi Komatsu Masahiro Fujita Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks. 3001-3008 2003 86-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 http://search.ieice.org/bin/summary.php?id=e86-a_12_3001 db/journals/ieiceta/ieiceta86.html#KomatsuF03

Thanyapat Sakunkonchak Satoshi Komatsu Masahiro Fujita Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams. 3192-3199 2003 86-A IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 12 http://search.ieice.org/bin/summary.php?id=e86-a_12_3192 db/journals/ieiceta/ieiceta86.html#SakunkonchakKF03

Ronald C. Arkin Masahiro Fujita Tsuyoshi Takagi Rika Hasegawa An ethological and emotional basis for human-robot interaction. 191-201 2003 42 Robotics Auton. Syst. 3-4 https://doi.org/10.1016/S0921-8890(02)00375-5 db/journals/ras/ras42.html#ArkinFTH03

Satoshi Komatsu Masahiro Fujita Irredundant address bus encoding techniques based on adaptive codebooks for low power. 9-14 2003 ASP-DAC https://doi.org/10.1145/1119772.1119775 conf/aspdac/2003 db/conf/aspdac/aspdac2003.html#KomatsuF03 Farzan Fallah Indradeep Ghosh Masahiro Fujita Event-driven observability enhanced coverage analysis of C programs for functional validation. 123-128 2003 ASP-DAC https://doi.org/10.1145/1119772.1119797 conf/aspdac/2003 db/conf/aspdac/aspdac2003.html#FallahGF03 Hiroshi Saito Hiroshi Nakamura Masahiro Fujita Takashi Nanya Logic optimization for asynchronous speed independent controllers using transduction method. 197-202 2003 ASP-DAC https://doi.org/10.1145/1119772.1119811 conf/aspdac/2003 db/conf/aspdac/aspdac2003.html#SaitoNFN03 Rajesh K. Gupta 0001 Shishpal Rawat Sandeep K. Shukla Brian Bailey Daniel K. Beece Masahiro Fujita Carl Pixley John O'Leary Fabio Somenzi Formal verification - prove it or pitch it. 710-711 2003 conf/dac/2003 DAC https://doi.org/10.1145/775832.776013 db/conf/dac/dac2003.html#GuptaRSBBFPOS03 Edmund M. Clarke Masahiro Fujita David P. Gluch Model Checking for Dependable Software-Intensive Systems. 764 2003 conf/dsn/2003 DSN https://doi.ieeecomputersociety.org/10.1109/DSN.2003.10001 db/conf/dsn/dsn2003.html#ClarkeFG03 Masahiro Fujita Satoshi Komatsu Hiroshi Saito Kenshu Seto Thanyapat Sakunkonchak Yoshihisa Kojima Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. 279 2003 conf/hicss/2003 HICSS https://doi.org/10.1109/HICSS.2003.1174810 https://doi.ieeecomputersociety.org/10.1109/HICSS.2003.1174810 db/conf/hicss/hicss2003.html#FujitaKSSSK03 Yoshihiro Kuroki Masahiro Fujita Tatsuzo Ishida Ken'ichiro Nagasaka Jin'ichi Yamaguchi A small biped entertainment robot exploring attractive applications. 471-476 2003 conf/icra/2003 ICRA db/conf/icra/icra2003.html#KurokiFINY03 https://doi.org/10.1109/ROBOT.2003.1241639 Masahiro Fujita Yoshihiro Kuroki Tatsuzo Ishida Toshi T. Doi Autonomous behavior control architecture of entertainment humanoid robot SDR-4X. 960-967 2003 IROS https://doi.org/10.1109/IROS.2003.1250752 https://www.wikidata.org/entity/Q56410321 conf/iros/2003 db/conf/iros/iros2003.html#FujitaKID03 Masahiro Fujita Kohtaro Sabe Yoshihiro Kuroki Tatsuzo Ishida Toshi T. Doi SDR-4X II: A Small Humanoid as an Entertainer in Home Environment. 355-364 2003 ISRR https://doi.org/10.1007/11008941_38 conf/isrr/2003 db/conf/isrr/isrr2003.html#FujitaSKID03 Hiroshi Saito Kenshu Seto Yoshihisa Kojima Satoshi Komatsu Masahiro Fujita Engineering Changes in Field Modifiable Architectures. 87-94 2003 conf/memocode/2003 MEMOCODE https://doi.ieeecomputersociety.org/10.1109/MEMOCODE.2003.10001 http://dl.acm.org/citation.cfm?id=823852 db/conf/memocode/memocode2003.html#SaitoSKKF03 Tetsuro Ogi Toshio Yamada Michitaka Hirose Masahiro Fujita Kazuto Kuzuu High Presence Remote Presentation in the Shared Immersive Virtual World. 289-290 2003 conf/vr/2003 VR https://doi.org/10.1109/VR.2003.1191168 https://doi.ieeecomputersociety.org/10.1109/VR.2003.1191168 db/conf/vr/vr2003.html#OgiYHFK03

Rajarshi Mukherjee Jawahar Jain Koichiro Takayama Jacob A. Abraham Donald S. Fussell Masahiro Fujita Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. 95-101 2002 21 Formal Methods Syst. Des. 1 db/journals/fmsd/fmsd21.html#MukherjeeJTAFF02 https://doi.org/10.1023/A:1016096020556

Yoshihiro Kuroki Tatsuzo Ishida Jin'ichi Yamaguchi Masahiro Fujita Toshi T. Doi A Small Biped Entertainment Robot. 6-12 2002 14 J. Robotics Mechatronics 1 https://doi.org/10.20965/jrm.2002.p0006 db/journals/jrm/jrm14.html#KurokiIYFD02

Edmund M. Clarke Masahiro Fujita Sreeranga P. Rajan Thomas W. Reps Subash Shankar Tim Teitelbaum Program slicing for VHDL. 125-137 2002 4 Int. J. Softw. Tools Technol. Transf. 1 https://doi.org/10.1007/s100090100069 db/journals/sttt/sttt4.html#ClarkeFRRST02

Masahiro Fujita Takashi Kanai Hardware-Assisted Relief Texture Mapping. 2002 Eurographics (Short Presentations) https://doi.org/10.2312/egs.20021048 conf/eurographics/2002short db/conf/eurographics/eg-short2002.html#FujitaK02 Thanyapat Sakunkonchak Masahiro Fujita Verification of Event-Based Synchronization of SpecC Description Using Difference Decision Diagrams. 369 2002 conf/forte/2002 FORTE https://doi.org/10.1007/3-540-36135-9_25 db/conf/forte/forte2002.html#SakunkonchakF02 Masao Kubo Masahiro Fujita Debug methodology for arithmetic circuits on FPGAs. 236-242 2002 FPT https://doi.org/10.1109/FPT.2002.1188687 conf/fpt/2002 db/conf/fpt/fpt2002.html#KuboF02 Satoshi Komatsu Yoshihisa Kojima Hiroshi Saito Kenshu Seto Masahiro Fujita Field modifiable architecture with FPGAs and its design methodology. 382-385 2002 FPT https://doi.org/10.1109/FPT.2002.1188716 conf/fpt/2002 db/conf/fpt/fpt2002.html#KomatsuKSSF02 Hiroshi Saito Takaya Ogawa Thanyapat Sakunkonchak Masahiro Fujita Takashi Nanya An equivalence checking methodology for hardware oriented C-based specifications. 139-144 2002 HLDVT https://doi.org/10.1109/HLDVT.2002.1224443 https://doi.ieeecomputersociety.org/10.1109/HLDVT.2002.1224443 conf/hldvt/2002 db/conf/hldvt/hldvt2002.html#SaitoOSFN02 Yoshihisa Kojima Hiroshi Saito Kenshu Seto Satoshi Komatsu Masahiro Fujita Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. 103-108 2002 conf/iwls/2002 IWLS db/conf/iwls/iwls2002.html#KojimaSSKF02 Hiroshi Saito Hiroshi Nakamura Masahiro Fujita Takashi Nanya Logic Optimization for Asynchronous SI Controllers using Transduction Method. 245-250 2002 conf/iwls/2002 IWLS db/conf/iwls/iwls2002.html#SaitoNFN02 Hiroshi Nakamura Takanori Arai Masahiro Fujita Formal Verification of a Pipelined Processor with New Memory. 321-324 2002 conf/prdc/2002 PRDC https://doi.org/10.1109/PRDC.2002.1185653 https://doi.ieeecomputersociety.org/10.1109/PRDC.2002.1185653 db/conf/prdc/prdc2002.html#NakamuraAF02 Masahiro Fujita Sony Four Legged Robot League at RoboCup 2002. 469-476 https://doi.org/10.1007/978-3-540-45135-8_43 2002 conf/robocup/2002 RoboCup db/conf/robocup/robocup2002.html#Fujita02 Hiroaki Yoshida Motohiro Sera Masao Kubo Masahiro Fujita Simultaneous Circuit Transformation and Routing. 479-483 2002 conf/vlsid/2002 ASP-DAC/VLSI Design https://doi.org/10.1109/ASPDAC.2002.994966 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994966 https://dl.acm.org/doi/10.5555/832284.835432 db/conf/vlsid/vlsid2002.html#YoshidaSKF02

Masahiro Fujita AIBO: Toward the Era of Digital Creatures. 781-794 2001 20 Int. J. Robotics Res. 10 https://doi.org/10.1177/02783640122068092 db/journals/ijrr/ijrr20.html#Fujita01

Jawahar Jain Ingo Wegener Masahiro Fujita A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. 1289-1290 2001 50 IEEE Trans. Computers 11 https://doi.org/10.1109/12.966501 http://doi.ieeecomputersociety.org/10.1109/12.966501 db/journals/tc/tc50.html#JainWF01

Indradeep Ghosh Masahiro Fujita Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. 402-415 2001 20 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/43.913758 db/journals/tcad/tcad20.html#GhoshF01

Masahiro Fujita Gabriel Costa Rika Hasegawa Tsuyoshi Takagi Jun Yokono Hideki Shimomura Architecture and preliminary experimental results for emotionally grounded symbol acquisition. 35-36 2001 conf/agents/2001 Agents https://doi.org/10.1145/375735.375851 db/conf/agents/agents2001.html#FujitaCHTYS01 Ronald C. Arkin Masahiro Fujita Tsuyoshi Takagi Rika Hasegawa Ethological Modeling and Architecture for an Entertainment Robot. 453-458 2001 conf/icra/2001 ICRA db/conf/icra/icra2001.html#ArkinFTH01 https://doi.org/10.1109/ROBOT.2001.932592 Tatsuzo Ishida Yoshihiro Kuroki Jin'ichi Yamaguchi Masahiro Fujita Toshi T. Doi Motion entertainment by a small humanoid robot based on OPEN-R. 1079-1086 2001 IROS https://doi.org/10.1109/IROS.2001.976312 conf/iros/2001 db/conf/iros/iros2001.html#IshidaKYFD01 Masahiro Fujita Hiroshi Nakamura The standard SpecC language. 81-86 2001 conf/isss/2001 ISSS db/conf/isss/isss2001.html#FujitaN01 https://doi.ieeecomputersociety.org/10.1109/ISSS.2001.957917 https://doi.org/10.1145/500001.500019 Wolfgang Rosenstiel Brian Bailey Masahiro Fujita Guang R. Gao Rajesh K. Gupta 0001 Preeti Ranjan Panda New Design Paradigms: What Needs to be Standardized?. 94 2001 conf/isss/2001 ISSS db/conf/isss/isss2001.html#RosenstielBFGGP01 https://doi.ieeecomputersociety.org/10.1109/ISSS.2001.10000 https://doi.org/10.1145/500001.500023 Takashi Michikawa Takashi Kanai Masahiro Fujita Hiroaki Chiyokura Multiresolution Interpolation Meshes. 60-69 2001 conf/pg/2001 PG https://doi.org/10.1109/PCCGA.2001.962858 https://doi.ieeecomputersociety.org/10.1109/PCCGA.2001.962858 db/conf/pg/pg2001.html#MichikawaKFC01 Rajarshi Mukherjee Jawahar Jain Koichiro Takayama Masahiro Fujita Automatic partitioning for efficient combinatorial verification. 67-72 2000 conf/aspdac/2000 ASP-DAC https://doi.org/10.1145/368434.368521 https://doi.org/10.1109/ASPDAC.2000.835072 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2000.835072 db/conf/aspdac/aspdac2000.html#MukherjeeJTF00 Indradeep Ghosh Masahiro Fujita Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. 43-48 2000 conf/dac/2000 DAC https://doi.org/10.1145/337292.337309 db/conf/dac/dac2000.html#GhoshF00 Yuan Lu 0004 Jawahar Jain Edmund M. Clarke Masahiro Fujita Efficient variable ordering using aBDD based sampling. 687-692 2000 conf/dac/2000 DAC https://doi.org/10.1145/337292.337614 db/conf/dac/dac2000.html#LuJCF00 Gregory Hornby Seiichi Takamura Osamu Hanagata Masahiro Fujita Jordan B. Pollack Evolution of Controllers from a High-Level Simulator to a High DOF Robot. 80-89 https://doi.org/10.1007/3-540-46406-9_9 2000 conf/ices/2000 ICES db/conf/ices/ices2000.html#HornbyTHFP00 Masahiro Fujita Digital Creatures for Future Entertainment Robotics. 801-806 2000 conf/icra/2000 ICRA db/conf/icra/icra2000.html#Fujita00 https://doi.org/10.1109/ROBOT.2000.844149 Gregory Hornby Seiichi Takamura Jun Yokono Osamu Hanagata Takashi Yamamoto Masahiro Fujita Evolving Robust Gaits with AIBO. 3040-3045 2000 conf/icra/2000 ICRA db/conf/icra/icra2000.html#HornbyTYHYF00 https://doi.org/10.1109/ROBOT.2000.846489 Takashi Yamamoto Masahiro Fujita A quadruped robot platform with basic software for RoboCup-99 legged robot league. 1026-1031 2000 IROS https://doi.org/10.1109/IROS.2000.893154 conf/iros/2000 db/conf/iros/iros2000.html#YamamotoF00 Vamsi Boppana Indradeep Ghosh Rajarshi Mukherjee Jawahar Jain Masahiro Fujita Hierarchical Error Diagnosis Targeting RTL Circuits. 436-441 2000 conf/vlsid/2000 VLSI Design https://doi.org/10.1109/ICVD.2000.812646 https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812646 db/conf/vlsid/vlsid2000.html#BoppanaGMJF00 Ankur Jain Vamsi Boppana Rajarshi Mukherjee Jawahar Jain Masahiro Fujita Michael S. Hsiao Testing, Verification, and Diagnosis in the Presence of Unknowns. 263-270 2000 conf/vts/2000 VTS https://doi.org/10.1109/VTEST.2000.843854 https://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843854 db/conf/vts/vts2000.html#JainBMJFH00

Ashok Sudarsanam Sharad Malik Masahiro Fujita A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library. 187-206 1999 4 Des. Autom. Embed. Syst. 2-3 https://doi.org/10.1023/A:1008913323623 db/journals/dafes/dafes4.html#SudarsanamMF99

Rajarshi Mukherjee Jawahar Jain Koichiro Takayama Masahiro Fujita Jacob A. Abraham Donald S. Fussell An efficient filter-based approach for combinational verification. 1542-1557 1999 18 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 https://doi.org/10.1109/43.806801 db/journals/tcad/tcad18.html#MukherjeeJTFAF99

Vamsi Boppana Sreeranga P. Rajan Koichiro Takayama Masahiro Fujita Model Checking Based on Sequential ATPG. 418-430 https://doi.org/10.1007/3-540-48683-6_36 1999 conf/cav/1999 CAV db/conf/cav/cav99.html#BoppanaRTF99 Edmund M. Clarke Masahiro Fujita Sreeranga P. Rajan Thomas W. Reps Subash Shankar Tim Teitelbaum Program Slicing of Hardware Description Languages. 298-312 https://doi.org/10.1007/3-540-48153-2_22 1999 conf/charme/1999 CHARME db/conf/charme/charme1999.html#ClarkeFRRST99 Sreeranga P. Rajan Masahiro Fujita Ashok Sudarsanam Sharad Malik Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. 2-6 1999 conf/codes/1999 CODES https://doi.org/10.1145/301177.301184 db/conf/codes/codes1999.html#RajanFSM99 Armin Biere Alessandro Cimatti Edmund M. Clarke Masahiro Fujita Yunshan Zhu Symbolic Model Checking Using SAT Procedures instead of BDDs. 317-320 1999 conf/dac/1999 DAC https://doi.org/10.1145/309847.309942 https://www.wikidata.org/entity/Q62041449 db/conf/dac/dac99.html#BiereCCFZ99 Vamsi Boppana Rajarshi Mukherjee Jawahar Jain Masahiro Fujita Pradeep Bollineni Multiple Error Diagnosis Based on Xlists. 660-665 1999 conf/dac/1999 DAC https://doi.org/10.1145/309847.310021 db/conf/dac/dac99.html#BoppanaMJFB99 Rajeev Murgai Masahiro Fujita On Reducing Transitions Through Data Modifications. 82- 1999 conf/date/1999 DATE https://doi.org/10.1109/DATE.1999.761101 https://doi.ieeecomputersociety.org/10.1109/DATE.1999.761101 https://doi.org/10.1145/307418.307457 db/conf/date/date1999.html#MurgaiF99 Rajarshi Mukherjee Jawahar Jain Koichiro Takayama Masahiro Fujita Jacob A. Abraham Donald S. Fussell An Efficient Filter-Based Approach for Combinational Verification. 132-137 1999 conf/date/1999 DATE https://doi.org/10.1109/DATE.1999.761108 https://doi.ieeecomputersociety.org/10.1109/DATE.1999.761108 https://doi.org/10.1145/307418.307475 db/conf/date/date1999.html#MukherjeeJTFAF99 Rajeev Murgai Fumiyasu Hirose Masahiro Fujita Speeding Up Look-up-Table Driven Logic Simulation. 385-397 1999 conf/ifip10-5/1999 VLSI db/conf/ifip10-5/ifip10-5-1999.html#MurgaiHF99 Rajeev Murgai Jawahar Jain Masahiro Fujita Efficient Scheduling Techniques for ROBDD Construction. 394-401 1999 conf/vlsid/1999 VLSI Design https://doi.org/10.1109/ICVD.1999.745188 https://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745188 db/conf/vlsid/vlsid1999.html#MurgaiJF99 Ankur Jain Michael S. Hsiao Vamsi Boppana Masahiro Fujita On the Evaluation of Arbitrary Defect Coverage of Test Sets. 426-432 1999 conf/vts/1999 VTS https://doi.org/10.1109/VTEST.1999.766699 https://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766699 db/conf/vts/vts1999.html#JainHBF99

Sreeranga P. Rajan Masahiro Fujita K. Yuan Mike Tien-Chien Lee ATM switch design by high-level modeling, formal verification and high-level synthesis. 554-562 1998 3 ACM Trans. Design Autom. Electr. Syst. 4 https://doi.org/10.1145/296333.296342 db/journals/todaes/todaes3.html#RajanFYL98

Masahiro Fujita Model Checking: Its Basics and Reality (Embedded Tutorial). 217-222 1998 conf/aspdac/1998 ASP-DAC db/conf/aspdac/aspdac98.html#Fujita98 https://doi.org/10.1109/ASPDAC.1998.669449 Rajeev Murgai Masahiro Fujita Arlindo L. Oliveira Using Complementation and Resequencing to Minimize Transitions. 694-697 1998 conf/dac/1998 DAC https://doi.org/10.1145/277044.277219 https://www.wikidata.org/entity/Q130984664 db/conf/dac/dac98.html#MurgaiFO98 Masahiro Fujita Sreeranga P. Rajan Alan J. Hu Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol. 281-295 1998 conf/fm/1998 FM-Trends db/conf/fm/fm1998.html#FujitaRH98 https://doi.org/10.1007/3-540-48257-1_18 Jawahar Jain William Adams Masahiro Fujita Sampling schemes for computing OBDD variable orderings. 631-638 1998 conf/iccad/1998 ICCAD https://doi.org/10.1145/288548.289099 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1998.743084 db/conf/iccad/iccad1998.html#JainAF98 Vamsi Boppana Masahiro Fujita Modeling the unknown! Towards model-independent fault and error diagnosis. 1094-1101 1998 conf/itc/1998 ITC https://doi.org/10.1109/TEST.1998.743310 https://doi.ieeecomputersociety.org/10.1109/TEST.1998.743310 db/conf/itc/itc1998.html#BoppanaF98 Sreeranga P. Rajan Masahiro Fujita Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. 552-557 1998 conf/vlsid/1998 VLSI Design https://doi.org/10.1109/ICVD.1998.646663 https://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646663 db/conf/vlsid/vlsid1998.html#RajanF98

Mike Tien-Chien Lee Yu-Chin Hsu Ben Chen Masahiro Fujita Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping. 319-338 1997 2 Des. Autom. Embed. Syst. 3-4 https://doi.org/10.1023/A:1008839720051 db/journals/dafes/dafes2.html#LeeHCF97

Masahiro Fujita Patrick C. McGeer Introduction to the Special Issue on Multi-Terminal Binary Decision Diagrams. 135-136 1997 10 Formal Methods Syst. Des. 2/3 db/journals/fmsd/fmsd10.html#FujitaM97 https://doi.org/10.1023/A:1008658421514

Edmund M. Clarke Kenneth L. McMillan Xudong Zhao 0005 Masahiro Fujita Jerry Chih-Yuan Yang Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. 137-148 1997 10 Formal Methods Syst. Des. 2/3 db/journals/fmsd/fmsd10.html#ClarkeMZFY97 https://doi.org/10.1023/A:1008695706493

Masahiro Fujita Patrick C. McGeer Jerry Chih-Yuan Yang Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation. 149-169 1997 10 Formal Methods Syst. Des. 2/3 db/journals/fmsd/fmsd10.html#FujitaMY97 https://doi.org/10.1023/A:1008647823331

Mike Tien-Chien Lee Vivek Tiwari Sharad Malik Masahiro Fujita Power analysis and minimization techniques for embedded DSP software. 123-135 1997 5 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/92.555992 db/journals/tvlsi/tvlsi5.html#LeeTMF97

Masahiro Fujita Koji Kageyama An Open Architecture for Robot Entertainment. 435-442 1997 conf/agents/1997 Agents db/conf/agents/agents97.html#FujitaK97 https://doi.org/10.1145/267658.267764 Sreeranga P. Rajan Masahiro Fujita ATM Switch Design: Parametric High-Level Modeling and Formal Verification. 437-450 1997 conf/amast/1997 AMAST db/conf/amast/amast97.html#RajanF97 https://doi.org/10.1007/BFb0000488 Rajat Aggarwal Rajeev Murgai Masahiro Fujita Speeding up technology-independent timing optimization by network partitioning. 83-90 1997 conf/iccad/1997 ICCAD https://doi.org/10.1109/ICCAD.1997.643375 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1997.643375 https://dl.acm.org/citation.cfm?id=266431 db/conf/iccad/iccad1997.html#AggarwalMF97 Alan J. Hu Masahiro Fujita Chris Wilson Formal Verification of the HAL S1 System Cache Coherence Protocol. 438-444 1997 conf/iccd/1997 ICCD db/conf/iccd/iccd97.html#HuFW97 https://doi.org/10.1109/ICCD.1997.628906 https://doi.ieeecomputersociety.org/10.1109/ICCD.1997.628906 Jawahar Jain Amit Narayan Masahiro Fujita Alberto L. Sangiovanni-Vincentelli A Survey of Techniques for Formal Verification of Combinational Circuits. 445-454 1997 conf/iccd/1997 ICCD db/conf/iccd/iccd97.html#JainNFS97 https://doi.org/10.1109/ICCD.1997.628907 https://doi.ieeecomputersociety.org/10.1109/ICCD.1997.628907 Masahiro Fujita Koji Kageyama A proposal of a quadruped robot platform for RoboCup. 1997 IROS https://doi.org/10.1109/IROS.1997.656810 conf/iros/1997 db/conf/iros/iros1997.html#FujitaK97 Jawahar Jain Amit Narayan Masahiro Fujita Alberto L. Sangiovanni-Vincentelli Formal Verification of Combinational Circuit. 218-225 1997 conf/vlsid/1997 VLSI Design https://doi.org/10.1109/ICVD.1997.568079 https://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568079 db/conf/vlsid/vlsid1997.html#JainNFS97 Rajeev Murgai Masahiro Fujita Some Recent Advances in Software and Hardware Logic Simulation. 232-238 1997 conf/vlsid/1997 VLSI Design https://doi.org/10.1109/ICVD.1997.568081 https://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568081 db/conf/vlsid/vlsid1997.html#MurgaiF97

Kiyoshi Ohishi Masaru Miyazaki Masahiro Fujita Hybrid Position and Force Control Without Force Sensor. 226-234 1996 8 J. Robotics Mechatronics 3 https://doi.org/10.20965/jrm.1996.p0226 db/journals/jrm/jrm8.html#OhishiMF96

Masahiro Fujita Verification of Arithmetic Circuits by Comparing Two Similar Circuits. 159-168 1996 conf/cav/1996 CAV db/conf/cav/cav96.html#Fujita96 https://doi.org/10.1007/3-540-61474-5_66 Mike Tien-Chien Lee Yu-Chin Hsu Ben Chen Masahiro Fujita Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. 585-590 1996 conf/dac/1996 DAC https://doi.org/10.1145/240518.240629 db/conf/dac/dac96.html#LeeHCF96 Jawahar Jain Amit Narayan C. Coelho 0001 Sunil P. Khatri Alberto L. Sangiovanni-Vincentelli Robert K. Brayton Masahiro Fujita Decomposition Techniques for Efficient ROBDD Construction. 419-434 1996 conf/fmcad/1996 FMCAD db/conf/fmcad/fmcad1996.html#JainNCKSBF96 https://doi.org/10.1007/BFb0031825 Amit Narayan Jawahar Jain Masahiro Fujita Alberto L. Sangiovanni-Vincentelli Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. 547-554 1996 conf/iccad/1996 ICCAD https://doi.org/10.1109/ICCAD.1996.569909 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1996.569909 https://dl.acm.org/citation.cfm?id=244894 db/conf/iccad/iccad1996.html#NarayanJFS96 Rajarshi Mukherjee Jawahar Jain Masahiro Fujita Jacob A. Abraham Donald S. Fussell On More Efficient Combinational ATPG Using Functional Learning. 107-110 1996 conf/vlsid/1996 VLSI Design https://doi.org/10.1109/ICVD.1996.489467 https://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489467 db/conf/vlsid/vlsid1996.html#MukherjeeJFAF96 Amit Narayan Sunil P. Khatri Jawahar Jain Masahiro Fujita Robert K. Brayton Alberto L. Sangiovanni-Vincentelli A study of composition schemes for mixed apply/compose based construction of ROBDDs. 249-253 1996 conf/vlsid/1996 VLSI Design https://doi.org/10.1109/ICVD.1996.489494 https://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489494 db/conf/vlsid/vlsid1996.html#NarayanKJFBS96 Jawahar Jain Rajarshi Mukherjee Masahiro Fujita Advanced Verification Techniques Based on Learning. 420-426 1995 conf/dac/1995 DAC https://doi.org/10.1145/217474.217564 db/conf/dac/dac95.html#JainMF95 Rajarshi Mukherjee Jawahar Jain Masahiro Fujita VERIFUL: VERIfication using FUnctional Learning. 444-448 1995 ED&TC https://doi.org/10.1109/EDTC.1995.470358 https://doi.ieeecomputersociety.org/10.1109/EDTC.1995.470358 https://dl.acm.org/doi/10.5555/787258.787476 conf/date/1995 db/conf/date/edtc1995.html#MukherjeeJF95 Edmund M. Clarke Masahiro Fujita Xudong Zhao 0005 Hybrid decision diagrams. 159-163 1995 conf/iccad/1995 ICCAD https://doi.org/10.1109/ICCAD.1995.480007 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1995.480007 https://dl.acm.org/citation.cfm?id=224875 db/conf/iccad/iccad1995.html#ClarkeFZ95 Rajeev Murgai Masahiro Fujita Fumiyasu Hirose Logic synthesis for a single large look-up table. 415-424 1995 conf/iccd/1995 ICCD https://doi.org/10.1109/ICCD.1995.528842 https://doi.ieeecomputersociety.org/10.1109/ICCD.1995.528842 db/conf/iccd/iccd1995.html#MurgaiFH95 Mike Tien-Chien Lee Vivek Tiwari Sharad Malik Masahiro Fujita Power analysis and low-power scheduling techniques for embedded DSP software. 110-115 1995 conf/isss/1995 ISSS https://doi.org/10.1145/224486.224525 https://doi.org/10.1109/ISSS.1995.520621 https://doi.ieeecomputersociety.org/10.1109/ISSS.1995.520621 db/conf/isss/isss1995.html#LeeTMF95 Ben Chen Michihiro Yamazaki Masahiro Fujita Bug Identification of a Real Chip Design by Symbolic Model Checking. 132-136 1994 conf/eurodac/1994edac EDAC-ETC-EUROASIC db/conf/eurodac/eurodac1994.html#ChenYF94 https://doi.org/10.1109/EDTC.1994.326886 Yutaka Tamiya Yusuke Matsunaga Masahiro Fujita LP based cell selection with constraints of timing, area, and power consumption. 378-381 1994 conf/iccad/1994 ICCAD https://doi.org/10.1109/ICCAD.1994.629822 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1994.629822 https://dl.acm.org/citation.cfm?id=191499 db/conf/iccad/iccad1994.html#TamiyaMF94 Yuji Kukimoto Masahiro Fujita Robert K. Brayton A redesign technique for combinational circuits based on gate reconnections. 632-637 1994 conf/iccad/1994 ICCAD https://doi.org/10.1109/ICCAD.1994.629888 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1994.629888 https://dl.acm.org/citation.cfm?id=191601 db/conf/iccad/iccad1994.html#KukimotoFB94 Hitomi Sato Michihiro Yamazaki Masahiro Fujita YEPHCAD and FLORA: Logic Synthesis for Control and Datapath. 527-530 1994 conf/iccd/1994 ICCD db/conf/iccd/iccd1994.html#SatoYF94 https://doi.org/10.1109/ICCD.1994.331967 https://doi.ieeecomputersociety.org/10.1109/ICCD.1994.331967 Masahiro Fujita Jerry Chih-Yuan Yang Edmund M. Clarke Xudong Zhao 0005 Patrick C. McGeer Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams. 275-278 1994 conf/iscas/1994 ISCAS db/conf/iscas/iscas1994-1.html#FujitaYCZM94 https://doi.org/10.1109/ISCAS.1994.408808

Masahiro Fujita Hisanori Fujisawa Yusuke Matsunaga Variable ordering algorithms for ordered binary decision diagrams and their evaluation. 6-12 1993 12 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/43.184839 db/journals/tcad/tcad12.html#FujitaFM93

Edmund M. Clarke Kenneth L. McMillan Xudong Zhao 0005 Masahiro Fujita Jerry Chih-Yuan Yang Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. 54-60 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.164569 db/conf/dac/dac93.html#ClarkeMZFY93 Masahiro Fujita Shinji Kono Synthesis of Controllers from Interval Temporal Logic Specification. 242-245 1993 conf/iccd/1993 ICCD db/conf/iccd/iccd1993.html#FujitaK93 https://doi.org/10.1109/ICCD.1993.393373 https://doi.ieeecomputersociety.org/10.1109/ICCD.1993.393373 Takeshi Sakaguchi Masahiro Fujita Hiroshi Watanabe Fumio Miyazaki Motion Planning and Control for a Robot Performer. 925-931 1993 conf/icra/1993 ICRA (3) db/conf/icra/icra1993-3.html#SakaguchiFWM93 https://doi.org/10.1109/ROBOT.1993.292262 Kuang-Chien Chen Masahiro Fujita Efficient Sum-to-One Subsets Algorithm for Logic Optimization. 443-448 1992 conf/dac/1992 DAC http://portal.acm.org/citation.cfm?id=113938.149563 db/conf/dac/dac92.html#ChenF92 Masahiro Fujita Yuji Kukimoto Patching Method for Lookup-Table Type FPLs. 61-70 1992 conf/fpga/1992 FPL db/conf/fpga/fpga1992.html#FujitaK92 https://doi.org/10.1007/3-540-57091-8_30 Yuji Kukimoto Masahiro Fujita Rectification method for lookup-table type FPGA's. 54-61 1992 conf/iccad/1992 ICCAD https://doi.org/10.1109/ICCAD.1992.279397 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1992.279397 https://dl.acm.org/citation.cfm?id=304057 db/conf/iccad/iccad1992.html#KukimotoF92 Masahiro Fujita RTL Design Verification by Making Use of Datapath Information. 592-597 1992 conf/iccd/1992 ICCD db/conf/iccd/iccd1992.html#Fujita92 https://doi.org/10.1109/ICCD.1992.276219 https://doi.ieeecomputersociety.org/10.1109/ICCD.1992.276219 Kiyoshi Ohishi Masaru Miyazaki Masahiro Fujita Yasumasa Ogino Force control without force sensor based on mixed sensitivity H ∞ design method. 1356-1361 1992 ICRA https://doi.org/10.1109/ROBOT.1992.220161 https://doi.ieeecomputersociety.org/10.1109/ROBOT.1992.220161 conf/icra/1992 db/conf/icra/icra1992.html#OhishiMFO92 Kuang-Chien Chen Yusuke Matsunaga Saburo Muroga Masahiro Fujita A Resynthesis Approach for Network Optimization. 458-463 1991 conf/dac/1991 DAC https://doi.org/10.1145/127601.127712 db/conf/dac/dac91.html#ChenMMF91 Masahiro Fujita Yusuke Matsunaga Taeko Kakuda On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. 50-54 1991 EURO-DAC http://dl.acm.org/citation.cfm?id=951525 conf/eurodac/1991 db/conf/eurodac/euro-dac1991.html#FujitaMK91 Masahiro Fujita Yutaka Tamiya Yuji Kukimoto Kuang-Chien Chen Application of Boolean Unification to Combinational Logic Synthesis. 510-513 1991 conf/iccad/1991 ICCAD db/conf/iccad/iccad1991.html#FujitaTKC91 https://doi.org/10.1109/ICCAD.1991.185318 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1991.185318 Masahiro Fujita Yusuke Matsunaga Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. 560-563 1991 conf/iccad/1991 ICCAD db/conf/iccad/iccad1991.html#FujitaM91 https://doi.org/10.1109/ICCAD.1991.185332 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1991.185332 Kuang-Chien Chen Masahiro Fujita Concurrent Resynthesis for Network Optimization. 44-48 1991 conf/iccd/1991 ICCD db/conf/iccd/iccd1991.html#ChenF91 https://doi.org/10.1109/ICCD.1991.139841 https://doi.ieeecomputersociety.org/10.1109/ICCD.1991.139841 Zhen-Ping Lo Masahiro Fujita Behnam Bavarian Analysis of Neighborhood Interaction in Kohonen Neural Networks. 246-249 1991 conf/ipps/1991 IPPS db/conf/ipps/ipps1991.html#LoFB91 https://doi.org/10.1109/IPPS.1991.153786 https://doi.ieeecomputersociety.org/10.1109/IPPS.1991.153786

Hitomi Sato Yoshihide Sugiura Masahiro Fujita Speed tunable finite state machine compiler: Zephcad. 17-20 1990 14 Microprocess. Microsystems 1 https://doi.org/10.1016/0141-9331(90)90009-K https://www.wikidata.org/entity/Q121690518 db/journals/mam/mam14.html#SatoSF90

Atsunobu Hiraiwa Masahiro Fujita Shigeru Kurosu Shigeru Arisawa Makoto Inoue Implementation of ANN on RISC processor array. 677-688 1990 ASAP https://doi.org/10.1109/ASAP.1990.145502 conf/asap/1990 db/conf/asap/asap1990.html#HiraiwaFKAI90 Hiroshi Nakamura Yuji Kukimoto Masahiro Fujita Hidehiko Tanaka A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. 76-85 1990 conf/cav/1990 CAV db/conf/cav/cav1990.html#NakamuraKFT90 https://doi.org/10.1007/BFb0023721 Hitomi Sato Yoshihiro Yasue Yusuke Matsunaga Masahiro Fujita Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. 284-289 1990 conf/dac/1990 DAC https://doi.org/10.1145/123186.123276 db/conf/dac/dac90.html#SatoYMF90 Hiroshi Nakamura Yuji Kukimoto Masahiro Fujita Hidehiko Tanaka A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. 493-504 1990 CAV (DIMACS/AMS volume) conf/dimacs/1990a db/conf/dimacs/dimacs1990a.html#NakamuraKFT90 https://doi.org/10.1090/dimacs/003/30 Masahiro Fujita Yusuke Matsunaga Takeo Kakuda Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. 38-41 1990 conf/iccad/1990 ICCAD db/conf/iccad/iccad1990.html#FujitaMK90 https://doi.org/10.1109/ICCAD.1990.129834 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1990.129834 Yusuke Matsunaga Masahiro Fujita Takeo Kakuda Multi-Level Logic Minimization Across Latch Boundaries. 406-409 1990 conf/iccad/1990 ICCAD db/conf/iccad/iccad1990.html#MatsunagaFK90 https://doi.org/10.1109/ICCAD.1990.129938 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1990.129938 Hiroshi Nakamura Yuji Kukimoto Masahiro Fujita Hidehiko Tanaka Practical design assistance at register transfer level using a data path verifier. 99-102 1990 ICCD https://doi.org/10.1109/ICCD.1990.130171 https://doi.ieeecomputersociety.org/10.1109/ICCD.1990.130171 conf/iccd/1990 db/conf/iccd/iccd1990.html#NakamuraKFT90 Hitomi Sato Norikazu Takahashi Yusuke Matsunaga Masahiro Fujita Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams. 286-290 1990 ICCD https://doi.org/10.1109/ICCD.1990.130228 https://doi.ieeecomputersociety.org/10.1109/ICCD.1990.130228 conf/iccd/1990 db/conf/iccd/iccd1990.html#SatoTMF90 Yusuke Matsunaga Masahiro Fujita Multi-level logic optimization using binary decision diagrams. 556-559 1989 ICCAD https://doi.org/10.1109/ICCAD.1989.77012 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1989.77012 conf/iccad/1989 db/conf/iccad/iccad1989.html#MatsunagaF89 Hiroshi Nakamura Masaya Nakai Shinji Kono Masahiro Fujita Hidehiko Tanaka Logic Design Assistence Using Temporal Logic Based Language Tokio. 174-183 1989 conf/lp/1989 LP db/conf/lp/lp89.html#NakamuraNKFT89 https://doi.org/10.1007/3-540-53919-0_12 Masahiro Fujita Hisanori Fujisawa Nobuaki Kawato Evaluation and improvement of Boolean comparison method based on binary decision diagrams. 2-5 1988 ICCAD https://doi.org/10.1109/ICCAD.1988.122450 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1988.122450 conf/iccad/1988 db/conf/iccad/iccad1988.html#FujitaFK88 Masahiro Fujita Shinji Kono Hidehiko Tanaka Tohru Moto-Oka Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog. 695-709 1986 conf/iclp/1986 ICLP db/conf/iclp/iclp86.html#FujitaKTM86 https://doi.org/10.1007/3-540-16492-8_119 T. Aoyagi Masahiro Fujita Tohru Moto-Oka Temporal Logic Programming Language Tokio - Programming in Tokio. 128-137 1985 conf/lp/1985 LP db/conf/lp/lp85.html#AoyagiFM85 https://doi.org/10.1007/3-540-16479-0_13 Shinji Kono T. Aoyagi Masahiro Fujita Hidehiko Tanaka Implementation of Temporal Logic Programming Language Tokio. 138-147 1985 conf/lp/1985 LP db/conf/lp/lp85.html#KonoAFT85 https://doi.org/10.1007/3-540-16479-0_14 Masahiro Fujita Makoto Ishisone Hiroshi Nakamura Hidehiko Tanaka Tohru Moto-Oka Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis. 246-255 1985 conf/lp/1985 LP db/conf/lp/lp85.html#FujitaINTM85 https://doi.org/10.1007/3-540-16479-0_24 Masahiro Fujita Hidehiko Tanaka Tohru Moto-Oka Specifying Hardware in temporal Logic & Efficient Synthesis of State-Diagrams Using Prolog. 572-581 1984 conf/fgcs/1984 FGCS db/conf/fgcs/fgcs84.html#FujitaTM84

Masahiro Fujita Hidehiko Tanaka Tohru Moto-Oka Temporal Logic Based Hardware Description and Its Verification with Prolog. 195-203 1983 1 New Gener. Comput. 2 db/journals/ngc/ngc1.html#FujitaTM83 https://doi.org/10.1007/BF03037426 https://www.wikidata.org/entity/Q113906585

Jacob A. Abraham William Adams Rajat Aggarwal Mehrnaz Ahmadi Toyokazu Akiyama Shuichi Akizuki Bijan Alizadeh Mythri Alle Yuichi Ambe Daisuke Ando Yoshinori Ando Takeshi Aoki T. Aoyagi Daisuke Arai Takanori Arai Ryosuke Araki Shiori Arimura Shigeru Arisawa Ronald C. Arkin Kunihiro Asada Minoru Asada Koji Asami Makoto Aso Tomoaki Atsumi Brian Bailey M. Balakrishnan Yoshiaki Bando Yosuke Bando Ryohei Banno Behnam Bavarian Bernd Becker 0001 Daniel K. Beece Payman Behnam Valeria Bertacco V. Bertacoo Armin Biere Pradeep Bollineni Andrea Bonarini Vamsi Boppana Robert K. Brayton Brett Browning Zolboo Byambadorj Albert J. Causo Ben Chen I-Ming Chen 0001 Kuang-Chien Chen Hiroaki Chiyokura Thomas Christaller Alessandro Cimatti Edmund M. Clarke C. Coelho 0001 Gabriel Costa David W. Currie Saptarsi Das Leah P. Dickstein Yi Ding Toshi T. Doi Yukiyasu Domae Klaus Doppler Rolf Drechsler Wayne C. Drevets Farzan Fallah Xiushan Feng Görschwin Fey Toshiaki Fujimoto Hisanori Fujisawa Masashi Fujita Tomofumi Fujiwara Hironobu Fujiyoshi Masaki Fukuchi Kosuke Fukui Shinnosuke Fukumura Tetsuharu Fukushima Yasuo Furukawa Kazuma Furutani Donald S. Fussell Fei Gao Guang R. Gao Ruitao Gao Shanghua Gao Ganesh Garga Samaneh Ghandali Indradeep Ghosh David P. Gluch Akihiro Goda Gensuke Goto Rajesh K. Gupta 0001 Jens-Steffen Gutmann Finn Haedicke Osamu Hanagata Rintaro Haraguchi Rika Hasegawa Manabu Hashimoto Wataru Hatakeyama Kazuma Hatta Mitsuhiro Hattori Kengo Hayashi Akio Higo Yoshikazu Hirai Atsunobu Hiraiwa Atsushi Hirose Fumiyasu Hirose Michitaka Hirose Suguru Hondo Kazuo Hongo Ryuta Horie Gregory HornbyGregory S. Hornby Yukiko Hoshino Michael S. Hsiao Yu-Chin Hsu Alan J. Hu Tomoya Ichimura Yoshinori Ieda Yasuoki Iida Tetsuya Iizuka Masataka Ikeda Suguru Ikeda Takayuki Ikeda Shuhei Ikemoto Yuki Ikeya Eduardo Camilo InacioEduardo C. Inacio Robert B. Innis Hiroki Inoue Makoto Inoue Masatsugu Iribe Tatsuzo Ishida Shintaro Ishihara Yuji Ishikawa Makoto Ishisone Takahiko Ishizu Atsuo Isobe Satoshi Ito Shun Ito Yuki Itotani Katsutoshi Itoyama Kentaro Iwata Ankur Jain Jawahar Jain Christian Damsgaard Jensen Satoshi Jo Koji Kageyama Taeko Kakuda Takeo Kakuda Tetsushi Kamegawa Gal A. Kaminka Takashi Kanai Takuya Kaneko Junya Kani Sriram Karunagaran Kenta Kato Kiyoshi Kato Takehisa Kato Jiro Katto Tomohiro Kawanabe Yasunori Kawanami Ryosuke Kawanishi Nobuaki Kawato Kiyoto Kawauchi Sunil P. Khatri Hiroaki Kikuchi Yusuke Kimura Takeo Kishida Hidetomo Kobayashi Shin-ya KobayashiShinya Kobayashi Somayeh Sadeghi Kohan Osamu Koike Ryogo Koikel Yoshihisa Kojima Hirone Komatsu Satoshi Komatsu Kazuyuki Kon Shinji Kono Masashi Konyo Pekka Korpinen Jun Koyama Koji Koyamada Munehiro Kozuma Ratna Krishnamoorthy Masao Kubo Yuji Kukimoto Jitendra Kumar Yoshiyuki Kurokawa Yoshihiro Kuroki Shigeru Kurosu Kazuto Kuzuu Mark Kwan Mike Tien-Chien Lee Yeonbok Lee Shaowen Li Chen Bin Lin Fangzheng Lin Yu Liu Zhen-Ping Lo Guillermo Lopez Yuan Lu 0004 Mizuo Maeda Shuhei Maeda Yukio Maehashi Fumihiko Magata Sharad Malik Alan G. Mallinger Hratch Mangassarian Yuto Mano Hiromasa Masuda Anmol Mathur Daisuke Matsubayashi Motohiko Matsuda Nori Matsuda Ken Matsui Nobutaka Matsumoto Takeshi Matsumoto Yusuke Matsunaga Fumitoshi Matsuno Toru Matsuoka Takanori Matsuzaki Patrick C. McGeer Kenneth L. McMillan Takashi Michikawa Mohammad Mirzaei Alan Mishchenko Natasa Miskov-Zivanov Raj S. Mitra Ashish Mittal Hidekazu Miyairi Atsushi Miyamoto Takeshi Miyamoto Yukio Miyasaka Fumio Miyazaki Masaru Miyazaki Tohru Moto-Oka Kohei Mukaiyama Rajarshi Mukherjee Tsutomu Murakawa Rajeev Murgai Saburo Muroga James Myers Masakuni Nagano Ken'ichiro Nagasaka Tatsuya Nagatani Shuhei Nagatsuka Takashi Nakagawa Masaya Nakai Mizuki Nakajima Koji Nakamaru Hiroshi Nakamura S. K. Nandy 0001Soumitra Kumar Nandy Takashi Nanya Amit Narayan Ranjani Narayan Zainalabedin Navabi Nicola Nicolici Keitaro Niki Masakatsu Nishigaki Tasuku Nishihara Hiroki Nishikawa Akio Noda Kuniaki Noda Akito Nomura Jorji Nonaka Shinnosuke Nozaki Oliver Obst Tsukasa Ogasawara Takaya Ogawa Tetsuro Ogi Yasumasa Ogino Tomohiko Ogishi Kiyoshi Ohishi Tetsushi Ohki Takuro Ohmaru Kazuaki Ohshima Satoru Ohshita Satoru Okamoto Yuki Okamoto Yutaka Okazaki Kentaro Oku Haruhisa Okuda Takashi Okuda Hiroshi G. Okuno John O'Leary Arlindo L. Oliveira Keiji Onishi Atsuki Ono Kenji Ono Shohei Ono Tatsuya Onuki Takeshi Osada Kosuke Oshima Shin-ichi O'Uchi Preeti Ranjan Panda Victor W. Pike Carl Pixley Daniel Polani Jordan B. Pollack Jayaraj Poroor Mukul R. Prasad Ugo Di Profio Wei Qi Sreeranga P. Rajan Shishpal Rawat Matteo Sonza Reorda Thomas W. Reps Gustavo Alfonso Garcia Ricardez Alberto Rodriguez 0003 Wolfgang Rosenstiel Kaushik Roy 0001 Kohtaro Sabe Takahiro Saeki Karuna P. Sahoo Hiroshi Saito Takahiro Saito Takeshi Sakaguchi Masayuki Sakakura Naohisa Sakamoto Thanyapat Sakunkonchak Sahand Salamat Alberto L. Sangiovanni-Vincentelli Ayane Sano Omid Sarbishei Ryôichi Sasaki Shunsuke Sasaki Hiroyuki Sato Hiroyuki Sato 0002 Hitomi Sato Ryo Sato Hidemasa Sawabe Tsutomu Sawada Motohiro Sera Ayumi Serizawa Kenshu Seto Subash Shankar Reza Sharafinejad Akira Shiba Yoichi Shibata Satoru Shimizu Takashi Shimizu Toshihiko Shimizu Hideki Shimomura Yuya Shiomi Yutaka Shionoiri Hirokazu Shirado Takeharu Shirai Koji Shiratsuchi Masoud Shiroei Fumiyoshi Shoji Chi Chang Shuai Kazuyuki Shudo Sandeep K. Shukla Sasaki Shunsuke Elizabeth Sklar Fabio Somenzi Shuran Song Asutosh Srivastava Ashok Sudarsanam Koji Sugano Ayaka Sugimoto Genki Sugimoto Yoshihide Sugiura Heming Sun Jingyu Sun Hiroyuki Suzuki Yasutaka Suzuki Yosuke Suzuki Mahmoud Tabandeh Osamu Tabata Kenjiro Tadakuma Satoshi Tadokoro Naoki Taguchi Sajjad Taheri Kazuyoshi Takagi Tsuyoshi Takagi Kenta Takahashi Norikazu Takahashi Taro Takahashi Tomoichi Takahashi Seiichi Takamura Eri Takane Koichiro Takayama Tatsuya Takemori Susumu Takeuchi Yutaka Tamiya Hikaru Tamura Fumihide Tanaka Hidehiko Tanaka Motoyasu Tanaka Tomoki Tanemura Hideo Tanida Tim Teitelbaum Yoshimi Teshigawara Vivek Tiwari Toshimitsu Tsuboi Takashi Tsuchiya Toshiyuki Tsuchiya Naoaki Tsutsui Kota Uehara Wataru Uesugi Pascal Urard Keshavan Varadarajan Andreas G. Veneris Masayuki Wakizaka Qinhao Wang Eiichiro Watamura Hiroshi Watanabe Shigeru Watanabe Shota Watanabe John Wawrzynek Ingo Wegener Chris Wilson J. Y. Wu Shao Hui Wu Shunsuke Yajima Yuto Yakubo Mako Yamada Toshio Yamada Naoto Yamade Jin'ichi Yamaguchi Takahiro J. Yamaguchi Yukio Yamaguchi Takashi Yamamoto Takumi Yamamoto Tomonari Yamamoto Yoshitaka Yamamoto Tadakazu Yamanaka Shigeru Yamashita Michihiro Yamazaki Shunpei Yamazaki Jerry Chih-Yuan Yang Yu-Shen Yang Yoshihiro Yasue Tri Rung Yew Qingyang Yi Jun Yokono Seiichi Yoneda Yuta Yoneyama Hiroaki Yoshida Mizuho Yoshihira Ayako Yoshimura Junwei Yu Lu Yu 0003 Mingfei Yu K. Yuan Carlos A. Zarate Jr. Andy Zeng 0001 Xinpei Zhang Yi Zhang Xudong Zhao 0005 Yunshan Zhu Sami S. Zoghbi