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2020 – today
- 2022
[c5]John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger:
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. ISSCC 2022: 428-429
2010 – 2019
- 2011
- [c4]Don Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John J. Wuu:
An 8MB level-3 cache in 32nm SOI with column-select aliasing. ISSCC 2011: 258-260
2000 – 2009
- 2009
- [c3]Anant Singh, Michael Ciraula, Don Weiss, John J. Wuu, Philippe Bauser, Paul de Champs, Hamid Daghighian, David E. Fisch, Philippe Graber, Michel Bron:
A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology. ISSCC 2009: 460-461 - 2007
- [c2]J. Dorsey, S. Searles, Michael Ciraula, S. Johnson, N. Bujanos, D. Wu, M. Braganza, S. Meyers, E. Fang, R. Kumar:
An Integrated Quad-Core Opteron Processor. ISSCC 2007: 102-103
1990 – 1999
- 1999
- [c1]Michael Ciraula, Irwin W. Sandberg:
Uniform approximation of discrete-time nonlinear systems. IJCNN 1999: 611-616
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