<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<inproceedings key="conf/asscc/NarayananDYWOM14" mdate="2025-02-26">
<author>Aravind Tharayil Narayanan</author>
<author>Wei Deng 0001</author>
<author>Dongsheng Yang 0002</author>
<author>Rui Wu 0001</author>
<author orcid="0000-0002-1082-7672">Kenichi Okada 0001</author>
<author>Akira Matsuzawa</author>
<title>A 0.011 mm<sup>2</sup> PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI.</title>
<pages>285-288</pages>
<year>2014</year>
<booktitle>A-SSCC</booktitle>
<ee>https://doi.org/10.1109/ASSCC.2014.7008916</ee>
<crossref>conf/asscc/2014</crossref>
<url>db/conf/asscc/asscc2014.html#NarayananDYWOM14</url>
</inproceedings>
</dblp>
