10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.

Dingxin Xu Zezheng Liu Yifeng Kuai Hongye Huang Yuncheng Zhang Zheng Sun 0001 Bangan Liu Wenqian Wang Yuang Xiong Junjun Qiu Waleed Madany Yi Zhang 0092 Ashbir Aviat Fadila Atsushi Shirane Kenichi Okada 0001 10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. 192-194 2024 ISSCC https://doi.org/10.1109/ISSCC49657.2024.10454284 conf/isscc/2024 db/conf/isscc/isscc2024.html#XuLKHZSLWXQMZFSO24