<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<article key="journals/tcad/SenguptaBM17" mdate="2025-11-04">
<author orcid="0000-0002-8215-7903">Anirban Sengupta 0003</author>
<author orcid="0000-0002-6502-2695">Saumya Bhadauria</author>
<author>Saraju P. Mohanty</author>
<title>TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis.</title>
<pages>655-668</pages>
<year>2017</year>
<volume>36</volume>
<journal>IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.</journal>
<number>4</number>
<ee>https://doi.org/10.1109/TCAD.2016.2597232</ee>
<ee>https://www.wikidata.org/entity/Q114985347</ee>
<url>db/journals/tcad/tcad36.html#SenguptaBM17</url>
</article></dblp>
