close
Skip to content
View ArturBieniek4's full-sized avatar
12 followers · 19 following

Organizations

@kuznia-rdzeni

Block or report ArturBieniek4

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
ArturBieniek4/README.md

Hi 👋, I'm Artur

arturbieniek4

  • 📚 Computer Science engineering graduate at University of Wrocław my work my thesis

  • 🌱 I’m currently learning CPU core design, FPGAs, Networking, Advanced SQL

  • 🔭 I’m currently working on Vast.AI GPU rigs, generating branch predictors using LLMs, DRAM refresh rate hacking

Languages and Tools:

c cplusplus linux python systemverilog verilog verilator risc-v

Stats Top Languages

Pinned Loading

  1. BTS2026-CTF-Writeups BTS2026-CTF-Writeups Public

    Writeups (not official) by me & my team for Break The Syntax 2026 CTF

    PHP

  2. engineering-thesis engineering-thesis Public archive

    My engineering thesis about implementing force/release in Verilator

    TeX

  3. University University Public

    C 3

  4. verilator/verilator verilator/verilator Public

    Verilator open-source SystemVerilog simulator and lint system

    SystemVerilog 3.7k 844

  5. kuznia-rdzeni/coreblocks kuznia-rdzeni/coreblocks Public

    RISC-V out-of-order core for education and research purposes

    Python 92 27

  6. sha3x_cudaminer sha3x_cudaminer Public archive

    A fast SHA3X CUDA miner

    Rust