IEEE Design & Test of Computers, Volume 13

Volume 13, Number 1, 1996

Conference Reports

• 
  John W. Sheppard:
  SCC20 attracts IEC participation. IEEE Des. Test Comput. 13(1): 2- (1996)

Panel Summaries

• 
  Masaharu Imai, Eugenio Villar:
  ASPDAC 1995: HDL synthesizability and interoperability. IEEE Des. Test Comput. 13(1): 3-4 (1996)

Features

• 
  Yervant Zorian, Jan Hlavicka:
  Guest Editors' Introduction: East Meets West. IEEE Des. Test Comput. 13(1): 5-7 (1996)
• 
  Tibor Bartos, Norbert Fristacky:
  Verifying Timing Consistency in Formal Specifications. 8-15
• 
  Stanislaw J. Piestrak:
  Self-Checking Design in Eastern Europe. 16-25
• 
  Anatoly Prihozhy:
  Net Scheduling in High-Level Synthesis. 26-35
• 
  Sergiu Radu, Viorel Onofrei, Mihai Albulet:
  Interconnection Problems in Modern Computers. 36-46
• 
  Raimund Ubar:
  Test Synthesis with Alternative Graphs. 48-57

Special Features

• 
  Mick Tegethoff, Tom Chen:
  Sensitivity Analysis of Critical Parameters in Board Test. 58-63
• 
  Joseph A. Mielke:
  Frequency Domain Testing of ADCs. 64-69
• 
  Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth:
  Fast Power Estimation of Large Circuits. 70-78
• 
  Kenneth M. Thompson:
  Intel and the Myths of Test. 79-81

Author Guidelines

• 
  IEEE Design & Test of Computers. IEEE Des. Test Comput. 13(1): 82-83 (1996)

DATC Newsletter

• 
  Design Automation Technical Committee Newsletter. IEEE Des. Test Comput. 13(1): 84-85 (1996)

TTTC Newsletter

• 
  Test Technology Tc Newsletter. IEEE Des. Test Comput. 13(1): 86-87 (1996)

The Last Byte-NEW

• 
  Scott Davidson:
  Base 1 logic: A method for environmentally friendly PC design. IEEE Des. Test Comput. 13(1): 88- (1996)

Volume 13, Number 2, 1996

• 
  Kenneth D. Wagner, Yervant Zorian:
  EIC Message. IEEE Des. Test Comput. 13(2): 2- (1996)

Conference Reports

• 
  Vishwani D. Agrawal:
  1995 Asian Test Symposium carves a niche. IEEE Des. Test Comput. 13(2): 3- (1996)

Panel Summaries

• 
  Hugo De Man:
  Submicron design tools: problems and suppliers. IEEE Des. Test Comput. 13(2): 4, 91 (1996)
• 
  Ajit M. Prabhu, Richard L. Campbell:
  Management Perspectives in EDA. IEEE Des. Test Comput. 13(2): 5-7, 90-91 (1996)

Features

• 
  Bozena Kaminska, Bernard Courtois:
  Guest Editors' Introduction: Mixed Analog and Digital Systems. IEEE Des. Test Comput. 13(2): 8-9 (1996)
• 
  Thomas Olbrich, Andrew Richardson:
  Design and Self-Test for Switched-Current Building Blocks. 10-17
• 
  Ashok Balivada, Jin Chen, Jacob A. Abraham:
  Analog Testing with Time Response Parameters. 18-25
• 
  Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi:
  DC Built-In Self-Test for Linear Analog Circuits. 26-33
• 
  Yukiya Miura:
  Real-Time Current Testing for A/D Converters. 34-41

Special Features

• 
  Stephen Brown, Jonathan Rose:
  FPGA and CPLD Architectures: A Tutorial. 42-57
• 
  Raul San Martin, John P. Knight:
  Optimizing Power in ASIC Behavioral Synthesis. 58-70
• 
  Paul E. Landman, Renu Mehra, Jan M. Rabaey:
  An Integrated CAD Environment for Low-Power Design. 72-82
• 
  A D&T Roundtable Deep-Submicron Design. IEEE Des. Test Comput. 13(2): 83-89 (1996)

DATC Newsletter

• 
  Design Automation Technical Committee Newsletter. IEEE Des. Test Comput. 13(2): 93- (1996)

TTTC Newsletter

• 
  Test Technology Tc Newsletter. IEEE Des. Test Comput. 13(2): 94-95 (1996)

The Last Byte

• 
  Scott Davidson:
  A test puzzle for a TGIF morning. 96-

Volume 13, Number 3, 1996

News

• 
  News. IEEE Des. Test Comput. 13(3): 4, 109 (1996)

Panel Summaries

• 
  Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov:
  Panel Summaries. IEEE Des. Test Comput. 13(3): 6, 110-112 (1996)

Conference Reports

• 
  Gil Philips, Yervant Zorian, Charles W. Rosenthal, Bozena Kaminska:
  Conference Reports. IEEE Des. Test Comput. 13(3): 8, 113-144 (1996)

Features

• 
  Vijay K. Madisetti, Mark A. Richards:
  Guest Editors' Introduction: Advances in Rapid Prototyping of Digital Systems. IEEE Des. Test Comput. 13(3): 9-11 (1996)
• 
  Vijay K. Madisetti:
  Rapid Digital System Prototyping: Current Practice, Future Challenges. 12-22
• 
  James H. M. Malley:
  RASSP: Changing the Paradigm of Electronic-System Design. 23-31
• 
  Richard M. Sedmak, John S. Evans:
  Spanning the Product Life Cycle: RASSP DFT. 32-42
• 
  Carolyn Kuttner:
  Hardware-Software Codesign Using Processor Synthesis. 43-53
• 
  Lan-Rong Dung, Vijay K. Madisetti:
  Conceptual Prototyping of Scalable Embedded DSP Systems. 54-65
• 
  Sandi Habinc, Peter Sinander:
  Using VHDL for Board Level Simulation. 66-78

Special Features

• 
  Harald P. E. Vranken, Marc F. Witteman, Ronald C. van Wuijtswinkel:
  Design for Testability in Hardware-Software Systems. 79-87
• 
  Ramesh Karri, Karin Högstedt, Alex Orailoglu:
  Computer-Aided Design of Fault-Tolerant VLSI Systems. 88-96
• 
  Adam Cron:
  A D&T Special Report: P1149.4 Mixed-Signal Test Bus. 98-101
• 
  A D&T Roundtable: Deep-Submicron Test in cooperation with the Test Technology Technical Committee. IEEE Des. Test Comput. 13(3): 102-108 (1996)

DATC Newsletter

• 
  Design Automation Technical Committee Newsletter. IEEE Des. Test Comput. 13(3): 116-117 (1996)

TTTC Newsletter

• 
  Test Technology Tc Newsletter. IEEE Des. Test Comput. 13(3): 118-119 (1996)

Last Byte

• 
  Scott Davidson:
  How to achieve 95% fault coverage without really trying. IEEE Des. Test Comput. 13(3): 120- (1996)

Volume 13, Number 4, 1996

News

• 
  News. IEEE Des. Test Comput. 13(4): 3-4, 88 (1996)

Conference Reports

• 
  Bernard Courtois:
  Second Therminic Workshop. IEEE Des. Test Comput. 13(4): 5- (1996)

Keynotes

• 
  Harold S. Stone:
  Designing in the multimedia era. 6-7
• 
  Wojciech Maly:
  The future of IC design, testing, and manufacturing. 8, 89-91

Features

• 
  Stephen Brown:
  FPGA Architectural Research: A Survey. 9-15
• 
  Stephen Brown, Muhammad M. Khellah, Zvonko G. Vranesic:
  Minimizing FPGA Interconnect Delays. 16-23
• 
  Todd A. DeLong, Barry W. Johnson, Joseph A. Profeta III:
  A Fault Injection Technique for VHDL Behavioral-Level Models. 24-33
• 
  Jacob M. Velixon:
  Transmission Coefficient Correction for DACs. 34-39
• 
  Karim Arabi, Bozena Kaminska, Janusz Rzeszut:
  BIST for D/A and A/D Converters. 40-49
• 
  Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
  Circular Self-Test Path for FSMs. 50-60
• 
  Jerry M. Soden, Charles F. Hawkins:
  IDDQ Testing: Issues Present and Future. 61-65
• 
  Koji Nakamae, Homare Sakamoto, Hiromu Fujioka:
  How ATE Planning Affects LSI Manufacturing Cost. 66-73
• 
  A D&T Roundtable: Telecommunications System Design. IEEE Des. Test Comput. 13(4): 74-81 (1996)
• 
  IEEE Design & Test of Computers 1996 Annual Index, Volume 13. IEEE Des. Test Comput. 13(4): 82-85 (1996)

Author Guidelines

• 
  Author Guidelines IEEE Design & Test of Computers. IEEE Des. Test Comput. 13(4): 86-87 (1996)

DATC Newsletter

• 
  Design Automation Technical Committee Newsletter. IEEE Des. Test Comput. 13(4): 93- (1996)

TTTC Newsletter

• 
  Test Technology Tc Newsletter. IEEE Des. Test Comput. 13(4): 94-95 (1996)

The Last Byte

• 
  Robert C. Aitken:
  When tools cry wolf: Testability pitfalls of synthesized designs. 96-